Scalable and Near-Optimal Design Space Exploration for Embedded Systems
Seiten
2014
|
2014
Springer International Publishing (Verlag)
978-3-319-04941-0 (ISBN)
Springer International Publishing (Verlag)
978-3-319-04941-0 (ISBN)
This book describes scalable and near-optimal, processor-level design space exploration (DSE) methodologies. The authors present design methodologies for data storage and processing in real-time, cost-sensitive data-dominated embedded systems. Readers will be enabled to reduce time-to-market, while satisfying system requirements for performance, area, and energy consumption, thereby minimizing the overall cost of the final design.
Introduction & Motivation.- Reusable DSE methodology for scalable & near-optimal frameworks.- Part I Background memory management methodologies.- Development of intra-signal in-place methodology.- Pattern representation.- Intra-signal in-place methodology for non-overlapping scenario.- Intra-signal in-place methodology for overlapping scenario.- Part II Processing related mapping methodologies.- Design-time scheduling techniques DSE framework.- Methodology to develop design-time scheduling techniques under constraints.- Design Exploration Methodology for Microprocessor & HW accelerators.- Conclusions & Future Directions.
Erscheint lt. Verlag | 3.4.2014 |
---|---|
Zusatzinfo | XVII, 277 p. 80 illus., 2 illus. in color. |
Verlagsort | Cham |
Sprache | englisch |
Maße | 155 x 235 mm |
Gewicht | 631 g |
Themenwelt | Mathematik / Informatik ► Informatik ► Theorie / Studium |
Technik ► Elektrotechnik / Energietechnik | |
Schlagworte | Design Space Exploration • DSE for Embedded Systems • Embedded Programmable Processors • Memory Management Methodology • Memory Optimization Techniques • Scalable & Near-optimal DSE • Scalable & Near-optimal DSE |
ISBN-10 | 3-319-04941-0 / 3319049410 |
ISBN-13 | 978-3-319-04941-0 / 9783319049410 |
Zustand | Neuware |
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