Open Verification Methodology Handbook
Creating Testbenches in SystemVerilog and SystemC
Seiten
2009
Morgan Kaufmann Publishers In (Verlag)
978-0-12-374398-5 (ISBN)
Morgan Kaufmann Publishers In (Verlag)
978-0-12-374398-5 (ISBN)
- Titel wird leider nicht erscheinen
- Artikel merken
Functional verification is the art and science of demonstrating that an electronic design works correctly and is ready to move from the drawing board to manufacture. This book demonstrates the Advanced Verification Methodology from Mentor Graphics, a method for building reusable verification components and assembling them into complex testbenches.
Functional verification is the art and science of demonstrating that an electronic design works correctly and is ready to move from the drawing board to manufacture. Functionally verifying a complex design is a time consuming and expensive process. The means by which a design is functionally verified is to build a TESTBENCH, a piece of software which exercises the design and determines whether the design works correctly and whether or not sufficient testing has been done.
This book demonstrates, in a high-accessible, step-by-step manner, the Advanced Verification Methodology from Mentor Graphics, a methodology for building reusable verification components and assembling them into complex testbenches. Application of the AVM can increase verification productivity and increase confidence that a design has been successfully verified. The AVM includes a software library that is implemented in both SystemC and SystemVerilog, the two programming languages most commonly used for building testbenches.
Functional verification is the art and science of demonstrating that an electronic design works correctly and is ready to move from the drawing board to manufacture. Functionally verifying a complex design is a time consuming and expensive process. The means by which a design is functionally verified is to build a TESTBENCH, a piece of software which exercises the design and determines whether the design works correctly and whether or not sufficient testing has been done.
This book demonstrates, in a high-accessible, step-by-step manner, the Advanced Verification Methodology from Mentor Graphics, a methodology for building reusable verification components and assembling them into complex testbenches. Application of the AVM can increase verification productivity and increase confidence that a design has been successfully verified. The AVM includes a software library that is implemented in both SystemC and SystemVerilog, the two programming languages most commonly used for building testbenches.
Verification Principles; Introduction to the AVM; Fundamentals of Object-Oriented Programming; Introduction to Transaction-Level Modeling; AVM Mechanics; Testbench Fundamentals; Complete Testbenches; Stepwise Refinement; Modules in Testbenches; Randomization; AVM in SystemC and SystemVerilog; Graphic Notation; Naming Conventions; AVM Encyclopedia.
Erscheint lt. Verlag | 12.12.2009 |
---|---|
Reihe/Serie | Systems on Silicon |
Verlagsort | San Francisco |
Sprache | englisch |
Maße | 191 x 235 mm |
Themenwelt | Mathematik / Informatik ► Informatik ► Theorie / Studium |
Technik ► Elektrotechnik / Energietechnik | |
ISBN-10 | 0-12-374398-2 / 0123743982 |
ISBN-13 | 978-0-12-374398-5 / 9780123743985 |
Zustand | Neuware |
Haben Sie eine Frage zum Produkt? |
Mehr entdecken
aus dem Bereich
aus dem Bereich
Grundlagen – Anwendungen – Perspektiven
Buch | Softcover (2022)
Springer Vieweg (Verlag)
34,99 €
Eine Einführung in die Systemtheorie
Buch | Softcover (2022)
UTB (Verlag)
25,00 €