Completion Detection in Asynchronous Circuits

lt;b>Pallavi Srivastava holds a Ph.D. in Electronics Engineering from Taylor's University, Malaysia (2022). She is an innovative and passionate educator having nine years of experience in industry and academics. She received her Master of Technology in Control Systems from VJTI, Mumbai, India (2012), and Bachelor of Technology in Electronics and Communication Engineering from Uttar Pradesh Technical University, India (2009), both with first-class honors. Her Master's dissertation was focused on designing an observer for Quantum Systems using Contraction Theory which is a recently developed nonlinear control system tool. Her research work also includes the design of fractional order controllers for robotic manipulators. She has authored papers in peer-reviewed journals and international conferences. Currently, Pallavi is working on the asynchronous design of digital circuits and its application. More precisely, she is working towards developing a deterministic completion detection scheme for single-rail asynchronous circuits.

Introduction to asynchronous circuit design.- "Preliminary considerations for asynchronous circuit design.".- "Completion detection schemes for asynchronous design style".- Case Studies: Barrel shifter and binary adders.- "Generic Architecture of deterministic completion detection scheme".-  Architecture optimization using deterministic completion detection".- Simulations.