System Verilog Assertions and Functional Coverage

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Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He then worked at Data General, Intel (first Pentium design team) and after a route of a couple of startups, worked at Applied Micro and TSMC. He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs and at TSMC he released two industry standard Reference Flows that establish Reuse of Verification Environment from ESL to RTL. Lately, he has been researching 3DIC design verification challenges at TSMC which is where SystemVerilog Assertions played an instrumental role in stacked die SoC design verification.

Introduction.- System Verilog Assertions.- Immediate Assertions.- Concurrent Assertions - Basics (sequence, property, assert).- Sampled Value Functions   $rose, $fell.- Operators.- System Functions and Tasks.- Multiple clocks.- Local Variables.- Recursive property.- Detecting and using endpoint of a sequence.- 'expect'.- 'assume' and formal (static functional) verification.- Other important topics.- Asynchronous Assertions !!!.- IEEE-1800-2009 Features.- SystemVerilog Assertions LABs.- System Verilog Assertions - LAB Answers.- Functional Coverage.- Performance Implications of coverage methodology.- Coverage Options.