Advanced Logic Synthesis

Andre Inacio Reis is a Professor at the Institute of Informatics, UFRGS, Brazil, since 2000. He is a senior member of IEEE and ACM, and co-authored more than 200 academic papers and 10 granted USA patents. He received best paper awards from IFIP VLSI 1997, SBCCI 2013 and IWLS 2015. Prof. Andre Reis is actively involved with the organization of ACM/IEEE IWLS. Andre Reis is an advisor for Nangate Inc since 2005, and coordinated cooperation directly between UFRGS and Nangate, as well as among Nangate, UFRGS and six other partners during the European FP7 project Synaptic. The primary research interest of Andre Reis is EDA, focusing on design flow convergence, general purpose optimization (SAT, SMT, ILP), and scalability for large designs (through parallelism and EDA 3.0). Additional interests include technical writing of articles, patents, and intellectual property legal aspects. Prof. Andre Reis wrote more than 500 poems and received awards for poetry writing. Rolf Drechsler is head of Cyber-Physical Systems department at the German Research Center for Artificial Intelligence (DFKI) since 2011. Furthermore, he is a Full Professor at the Institute of Computer Science, University of Bremen, since 2001. Before, he worked for the Corporate Technology Department of Siemens AG, and was with the Institute of Computer Science, Albert-Ludwig University of Freiburg/Breisgau, Germany. Rolf Drechsler received the Diploma and Dr. Phil. Nat. degrees in computer science from the Goethe-University in Frankfurt/Main, Germany, in 1992 and, respectively, 1995. Rolf Drechsler focusses in his research at DFKI and in the Group for Computer Architecture, which he is heading at the Institute of Computer Science of the University of Bremen, on the development and design of data structures and algorithms with an emphasis on circuit and system design.

EDA3.0: Implications to Logic Synthesis.- Can parallel programming revolutionize EDA tools?.- Emerging Circuit Technologies: An Overview on the Next Generation of Circuits.- Physical Awareness starting at Technology-Independent Logic Synthesis.- Identifying Transparent Logic in Gate-Level Circuits.- Automated Pipeline Transformations with Fluid Pipelines.- Analysis of Incomplete Circuits using Dependency Quantied Boolean Formulas.- Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver.- A Branch-and-Bound-Based Minterm Assignment Algorithm for Synthesizing Stochastic Circuit.- Decomposition of Index Generation Functions Using a Monte Carlo Method.