Computer Principles and Design in Verilog HDL

Yamin Li, Professor, Department of Computer Science, Hosei University, Tokyo, Japan. Professor Li received his PhD in computer science from Tsinghua University in 1989. His research interests include computer arithmetic algorithms, computer architecture, CPU design, and parallel & distributed computing. He is a senior member of the IEEE and a member of the IEEE Computer Society. Professor Li has taught the courses of "Logic Circuit Design", "Assembly Language Programming", "Computer Organization and Design", "CPU Design in Verilog HDL", "Computer Architecture", and "Parallel & Distributed Systems" for more than 20 years, and has used FPGA boards and CAD/CAE tools to teach these courses since 1993. He has published more than 100 journal and conference papers, and developed a square root circuit at low cost and published it in IEEE ICCD'96 and ICCD'97.

List of Figures xv

List of Tables xxvii

Preface xxix

1 Computer Fundamentals and Performance Evaluation 1

2 A Brief Introduction to Logic Circuits and Verilog HDL 19

3 Computer Arithmetic Algorithms and Implementations 63

4 Instruction Set Architecture and ALU Design 111

5 Single-Cycle CPU Design in Verilog HDL 143

6 Exceptions and Interrupts Handling and Design in Verilog HDL 170

7 Multiple-Cycle CPU Design in Verilog HDL 192

8 Design of Pipelined CPU with Precise Interrupt in Verilog HDL 212

9 Floating-Point Algorithms and FPU Design in Verilog HDL 266

10 Design of Pipelined CPU with FPU in Verilog HDL 323

11 Memory Hierarchy and Virtual Memory Management 353

12 Design of Pipelined CPU with Caches and TLBs in Verilog HDL 386

13 Multithreading CPU and Multicore CPU Design in Verilog HDL 425

14 Input/Output Interface Controller Design in Verilog HDL 443

15 High-Performance Computers and Interconnection Networks 509

Bibliography 536

Index 539