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Source-Synchronous Networks-On-Chip

Circuit and Architectural Interconnect Modeling

Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra (Autoren)

Buch | Hardcover

143 Seiten

2013
Springer-Verlag New York Inc.
978-1-4614-9404-1 (ISBN)

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This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

Introduction.- Clock Distribution for fast Networks-on-Chip.- Fast Network-on-Chip Design.- Fast On-Chip Data transfer using Sinusoid Signals.- Conclusion and Future Work.

Zusatzinfo	10 Illustrations, color; 85 Illustrations, black and white; XIII, 143 p. 95 illus., 10 illus. in color.
Verlagsort	New York, NY
Sprache	englisch
Maße	155 x 235 mm
Themenwelt	Mathematik / Informatik ► Informatik ► Theorie / Studium
Themenwelt	Technik ► Elektrotechnik / Energietechnik
Schlagworte	Low-Jitter Clock for Network-on-Chip • networks-on-chip • NoC • NoC Interconnect • On-Chip Communication Architecture • Resonant Clocking • Source-synchronous Networks-on-Chip • System-on-Chip
ISBN-10	1-4614-9404-4 / 1461494044
ISBN-13	978-1-4614-9404-1 / 9781461494041
Zustand	Neuware