Network-on-Chip Architectures
Springer (Verlag)
978-94-007-3049-6 (ISBN)
MICRO-Architectural Exploration.- A Baseline NoC Architecture.- ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39].- RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40].- Exploring FaultoTolerant Network-on-Chip Architectures [37].- On the Effects of Process Variation in Network-on-Chip Architectures [45].- MACRO-Architectural Exploration.- The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15].- Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43].- A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44].- Digest of Additional NoC MACRO-Architectural Research.- Conclusions and Future Work.
Reihe/Serie | Lecture Notes in Electrical Engineering ; 45 |
---|---|
Zusatzinfo | XXII, 223 p. |
Verlagsort | Dordrecht |
Sprache | englisch |
Maße | 155 x 235 mm |
Themenwelt | Mathematik / Informatik ► Informatik ► Theorie / Studium |
Technik ► Elektrotechnik / Energietechnik | |
Schlagworte | Computer Architecture • energy efficiency • fault tolerance • Network-on-Chip • On-Chip Interconnects • Reliability |
ISBN-10 | 94-007-3049-7 / 9400730497 |
ISBN-13 | 978-94-007-3049-6 / 9789400730496 |
Zustand | Neuware |
Haben Sie eine Frage zum Produkt? |
aus dem Bereich