Principles of Semiconductor Network Testing (eBook)

Front Cover 1
Principles of Semiconductor Network Testing 4
Copyright Page 5
Contents 8
Foreword 12
Preface 14
Chapter 1. Diode and Transistor Operation 16
Introduction 16
1.1 Semiconductor Materials 18
1.2 Bipolar Transistors 21
1.3 MOS Transistors 30
References 36
Chapter 2. Integrated Circuit Test Basics 38
Introduction 38
2.1 Designing Integrated Circuits 39
2.2 Silicon Wafer Production 40
2.3 Test Limits Guardbanding 43
2.4 Wafer Test Hardware 46
2.5 Bonding and Packaging 49
2.6 Final Test 49
2.7 Quality Assurance (QA) Test 50
References 71
Chapter 3. Digital Logic Test 72
Introduction 72
3.1 Continuity Test 75
3.2 Shorts Test 75
3.3 Functional Test 76
3.4 lcc Test 76
3.5 Breakdown Voltage (VB) Test 77
3.6 VOH Test (High Level Output Voltage) 78
3.7 VOL Test (Low Level Output Voltage) 78
3.8 IIL Test (Low Level Input Current) 79
3.9 lIH Test (High Level Input Current) 79
3.10 IOZH Test (High Level Three-state Output Current) 80
3.11 IOZL Test (Low Level Three-state Output Current) 81
3.12 IOL (Saturation) Test (Low Output Saturation Current) 82
3.13 IOH (Saturation) Test (High Output Saturation Current) 82
3.14 Voltage Hysteresis (VHYS) Test 83
3.15 A Binary Search Algorithm 85
3.16 AC Testing Description 87
3.17 Propagation Delay Test (tPLH, tPHL, tPHZ, tPLZ) 88
3.18 Output Pulse Width (tw) Test 89
3.19 Rise and Fall Time Test (tR, tF) 90
3.20 Setup Time Test (tsu) 90
3.21 Hold Time Test (tH) 90
3.22 Removal Time (tREM)or Recovery Time (tREC) Test 91
3.23 Noise in Digital Circuits 91
References 97
Chapter 4. Noise Identification 98
Introduction 98
4.1 Grounding 100
4.2 General Guidelines for Grounding 102
4.3 Resistor Noise 103
4.4 Inductor Noise 104
4.5 Capacitor Noise 105
4.6 1/f or Flicker Noise 107
4.7 Shot Noise 107
4.8 Thermal Noise 108
4.9 Popcorn (Burst) Noise 108
4.10 Contact Noise 109
4.11 Using Capacitors for Suppressing Noise 110
4.12 Decoupling 110
4.13 Facts about Power Supplies 111
4.14 Suppressing Noise Created by Capacitive Load 113
4.15 Noise in Bipolar Transistors 114
References 114
Chapter 5. Operational Amplifier 116
Introduction 116
5.1 Ideal Behavior of an Op Amp 118
5.2 Feedback Configurations 119
5.3 Basic Op Amp Internal Structure 119
5.4 Common Mode Signal 123
5.5 Input Impedance 125
5.6 Single-ended Output 125
5.7 Input Bias Current (IB) 126
5.8 Slew Rate (SR) 126
5.9 Op Amp DC Measurement (Nulling Circuit) 129
5..10 VOS Test (Input Offset Voltage) 130
5.11 VOS Test Using Nulling Circuit 131
5.12 lOS Test (Input Offset Current) 132
5.13 VON Test (Negative Output Voltage Swing) 133
5.14 VOP Test (Positive Output Voltage Swing) 134
5.15 CMRR Test (Common Mode Rejection Ratio) 134
5.16 SR Test (Slew Rate) 136
5.17 AV (Gain) Test 136
5.18 PSRR Test (Power Supply Rejection Ratio) 137
5.19 Noise in Op-amp Circuits (Crosstalk) 138
5.20 Oscillation 138
5.21 Noise in Different Types of Operational Amplifiers 140
5.22 The Decibel 143
References 143
Chapter 6. Data Acquisition Devices 146
Introduction 146
6.1 Field of Application 148
6.2 Definition of Terms 148
6.3 Operation of a 4-Bit Converter 157
6.4 Conversion Operation 158
6.5 A/D and D/A Test Description 160
6.6 IIH Test (Logical "1" Input Current) 173
6.7 IlL Test (Logical "0" Output Current) 174
6.8 IOZL Test (Three-state Low Level Output Leakage) 174
6.9 IOZH Test (Three-state High Level Output Leakage) 175
6.10 VOH Test (Logic "1" Output Voltage) 175
6.11 VOL Test (Logic "0" Output Voltage) 176
6.12 ICC/IDD Test (Power Supply Current) 176
6.13 lcc+R Test (Combined Icc+R Current) 177
6.14 lIN(1) Test (Analog High on Channel Input Current) while Clock is On 177
6.15 lIN(0) Test (Analog Low on Channel Input Current) while Clock is On 178
6.16 lIN(1) Test (Analog High on Channel Input Current) while Clock is Off 178
6.17 IIN(0) Test (Analog Low on Channel Input Current) while Clock is Off 178
6.18 Functional Test 179
6.19 TwALE Test (ALE Pulse Width) 180
6.20 RES Test (Resolution Test) 180
6.21 Nonlinearity Test 181
6.22 RL Test (Ladder Resistance Test) 182
6.23 Tws Test (Minimum Start Pulse Width) 182
6.24 Ts Test (Minimum Address Setup Time) 183
6.25 TH Test (Minimum Address Hold Time) 183
6.26 TD Test (Analog MUX Delay Time from ALE) 183
6.27 TH1, TH0 Test (OE Control to Q Logic State) 184
6.28 TH1, TH0 Test (OE Control to High-Z) 184
6.29 Tc Test (Conversion Time) 185
6.30 Fc Test (Clock Frequency) 185
References 185
Chapter 7. Digital Signal Processing 188
Introduction 188
7.1 Anti-aliasing Filter 189
7.2 Sample-and-Hold Module 190
7.3 Audio Digitizer 190
7.4 Function Generator and Signal Properties 190
7.5 Fourier Series and Fourier Transforms 192
7.6 Signal Conversion 195
7.7 Sampling Rate 198
7.8 Errors 200
References 202
Chapter 8. CODEC (Coder/Decoder) 204
Introduction 204
8.1 Frame Concept 205
8.2 Companding Rules in Communication 207
8.3 C-Message and P-Message 209
8.4 Unit of Noise Power 210
8.5 Standards for CODEC 213
8.6 Device Minimum Capability 213
8.7 Basic Modulations in Telecommunication 213
8.8 CODEC Requirements 214
8.9 Introduction to CODEC Testing 214
8.10 Single-tone CODEC Testing (Analog Method) 215
8.11 Multitone CODEC Testing 219
8.12 Full-channel and Half-channel Tests 220
8.13 lCC, IDD Test (Supply Current) 220
8.14 CODEC Dynamic Tests--Encoder Section 220
8.15 CODEC Dynamic Tests--Decoder Section 222
References 223
Index 224