Handbook of Memristor Networks (eBook)

Preface 5
Contents 11
1 The Fourth Element 15
1 Axiomatic Definition of Circuits Elements 15
2 (v(?)-i(?)) Circuit Elements 20
3 Complexity Metric of Circuit Elements 22
4 Fingerprint of Memristors 22
5 Concluding Remarks 26
References 26
2 If It’s Pinched It’s a Memristor 29
1 If It’s Pinched It’s a Memristor 30
1.1 First Man-Made Memristor 31
1.2 Pre-1948 Memristors 31
1.3 Pre-1970 Thin Oxide-Film Memristors 33
1.4 1971: Synthesized Memristors 35
1.5 Post-2000 Memristors 38
1.6 Organic Memristors 41
1.7 Biological Memristors 41
1.8 Plant Memristor 43
1.9 A Micro Kinetic Memristor 46
2 Three Memristor Representations 46
2.1 Extended Memristor 46
2.2 Generic Memristor 46
2.3 Ideal Memristor 48
3 Potassium and Sodium Ion Channels Are Generic Memristors 51
3.1 Pinched Hysteresis Loops Evolve with Frequency 54
3.2 Pinched Hysteresis Loops Degenerate to Straight Lines at High Frequencies 57
3.3 DC V-I Curves 59
4 Ideal Memristors Have Bizarre DC V-I Curves 61
4.1 Example 1: Memristor V-I “Rectifier” Curve 62
4.2 Example 2: Memristor Without a DC V-I Curve 62
4.3 The DC V-I Curve of an Ideal Memristor Is a Single Point (V, I) = (0, 0)! 64
5 Ideal Memristor: Four Guided Tours 66
5.1 Ideal Memristor Guided Tour 1 67
5.2 Ideal Memristor Guided Tour 2 68
5.3 Ideal Memristor Guided Tour 3 68
5.4 Ideal Memristor Guided Tour 4 68
5.5 All Ideal Memristors Are Non-volatile Analog Memories 72
5.6 Modelling Beck et al. “Bow-Tie” Loop 73
6 Generic Memristor: A Guided Walk 74
6.1 Non-volatile Binary Memory 76
6.2 How to Set and Reset Memory States? 78
6.3 Why Minimum Pulse Width and Minimum Pulse Amplitude? 78
6.4 A Bi-continuum Non-volatile Memory 79
6.5 Pinched Hysteresis Loop Need not Be Symmetric 80
7 Extended Memristors: A Glimpse 81
8 Locally-Active Memristors 87
8.1 A Locally-Active Memristor Oscillator 88
8.2 A One-Memristor Chaos Generator 90
8.3 A One-Memristor Oscillator 93
9 If It’s Not Pinched It’s Not a Memristor 94
10 Concluding Remarks 96
Appendix 99
References 100
3 Everything You Wish to Know About Memristors but Are Afraid to Ask 103
1 Some Nagging Questions About Memristors 103
2 Experimental Definition of Memristors 104
3 Ideal Memristors 109
4 Ideal Generic Memristor 112
4.1 Graphical Composition Method for Generating G(X) and  (x) from a Voltage-Controlled Ideal Memristor 113
4.2 Graphical Composition Method for Generating R(X) and  (x) from a Current-Controlled Ideal Memristor 115
4.3 Ideal Memristors and Its Siblings Give Identical Pinched Hysteresis Loops 117
4.4 Recovering Ideal Memristor from Its Siblings 118
5 Generic Memristor 119
6 Extended Memristor 129
7 Pinched Hysteresis Loop Fingerprints 131
8 Coincident Zero-Crossing Signatures 133
8.1 Passive Memristors Have Identical Zero Crossings 138
8.2 Passive Memristors Have Zero Phase Shifts 138
9 POP: Power—Off Plot 139
10 DC V-I Plots 144
10.1 Passive but Locally-Active Memristors 154
10.2 DC V-I Plots May Contain Unobservable Points 156
10.3 Two Stable Branches Through Origin Implies Non-volatile Binary Memory 157
10.4 Quasi DC V-I Plot 157
10.5 A Shoelace DC V-I Plot 157
11 Continuum-Memory Memristors 159
11.1 Pinched Hysteresis Loop at Extreme Low Frequencies 161
11.2 Quasi DC V-I Plot Is not DC V-I Plot! 162
12 Concluding Remarks 164
Appendix 167
References 170
4 Aftermath of Finding the Memristor 172
References 176
5 Three Fingerprints of Memristor 177
1 Introduction 177
2 Generic Definition of Memristor 178
3 Memristor Fingerprints 180
3.1 Memristor Fingerprint 1: Pinched Hysteresis Loop 180
3.2 Memristor Fingerprint 2: Hysteresis Lobe Area Decreases as Frequency Increases 183
3.3 Memristor Fingerprint 3: Pinched Hysteresis Loop Shrinks to a Single-Valued Function at Infinite Frequency 188
4 Memductance Limiting-Slope Calculation Methods 190
4.1 Memductance Limiting-Slope Calculation Method 1 190
4.2 Memductance Limiting-Slope Calculation Method 2 191
5 Transversality at the Origin 196
5.1 Example of Transversal Pinched Hysteresis Loop 197
5.2 Examples of Non-transversal Pinched Hysteresis Loop 198
6 Conclusion 205
References 208
6 Resistance Switching Memories are Memristors 209
1 Pinched Hysteresis Loops 210
2 Continuum of Non-volatile Memories 216
3 -q Curve and Memristance Versus State Maps are Equivalent Memristor Representations 217
4 Resistance Versus State Map and State Equation 219
5 Correspondence Between Small-Signal Memristance and Chord Memristance 219
6 Ideal Memristor -q Curves for Binary Memories 221
7 Unfolding the Memristor 227
7.1 Non-volatile Memristors 232
7.2 Negative Resistance 233
7.3 Is Memristor Negative Resistance Real or Artifact? 234
8 Switching and Sensing Resistance Memory 235
9 Concluding Remarks 239
References 242
7 The Detectors Used in the First Radios were Memristors 243
1 Introduction 243
2 Cat's Whisker Detector Setup 246
3 Terminology 248
4 Experimental Results 249
4.1 Cohering Action 250
4.2 Multistable Memristive Behavior 250
4.3 Bistable Resistive RAM/Memristive Mode 252
5 Discussion 255
References 257
8 Why are Memristor and Memistor Different Devices? 258
1 Introduction 258
2 Memristor and Memistor are Different 259
2.1 Memristor 259
2.2 Memistor 261
3 Memristor-Based Memistor 263
3.1 Two Back-to-Back Series-Connected Memristors 263
3.2 Charge Versus Flux Relationship of the Composite Device with Two Back-to-Back Series-Connected Memristors 266
4 Widrow's Memistor is Not Well-Posed 268
5 More Distinctions Between Memistor and Memristor 273
6 Conclusion 275
References 275
9 The Art and Science of Constructing a Memristor Model: Updated 277
1 Introduction 278
2 Locally Active Memristor: Physical Principles Approach 281
3 Nonvolatile Titanium Dioxide Memristor: Measurement Approach 285
4 Nonvolatile Tantalum Pentoxide Memristor: State Variable Identification 288
5 Conclusions 293
References 293
10 Memristor, Hodgkin-Huxley, and Edge of Chaos 296
1 Introduction 296
2 Definition, Symbol, and Fingerprints 297
2.1 Memristor is Defined by a State-Dependent Ohm's Law 297
2.2 If It's Pinched It's a Memristor 300
2.3 Ideal Memristor 301
3 When is a Memristor Non-volatile? 303
4 Synapses Are Memristors 305
4.1 Learning with Memristors: Habituation 305
4.2 Learning with Memristors: LTP 307
5 Hodgkin-Huxley Axon is Made of Memristors 309
5.1 Anomalies of the Hodgkin-Huxley Axon Circuit Model 309
5.2 Deriving the DC V-I Characteristic of the Hodgkin-Huxley Axon 314
5.3 Deriving the Small-Signal Admittance of the Hodgkin-Huxley Axon 315
6 Neurons Are Poised Near the Edge of Chaos 318
6.1 Eigenvalues of Hodgkin-Huxley Axon Are Zeros of Y(s) 318
6.2 Action Potential Originates Near the Edge of Chaos 319
7 How Did I Connect Memristor to Hodgkin-Huxley? 321
References 322
11 Brains Are Made of Memristors 323
1 Introduction 323
2 Characterization of Pinched Hysteresis Loops 324
2.1 Examples of Pinched Hysteresis Loops of Potassium Memristor 326
2.2 Examples of Pinched Hysteresis Loops of Sodium Ion-Channel Memristor 328
2.3 Computation of Lobe Area of Pinched Hysteresis Loop via Riemann–Stieltjes Integral 333
2.4 Clockwise and Counter-Clockwise Orientation of the Pinch Hysteresis Loop of a Memristor 336
3 DC V-I Curves of the Potassium Ion-Channel Memristor, Sodium Ion-Channel Memristor and Memristive Hodgkin-Huxley Axon Circuit Model 342
4 Small-Signal Equivalent Circuits and Nyquist Plot of Ion-Channel Memristor 343
4.1 Small-Signal Equivalent Circuit and Nyquist Plot of the Potassium Ion-Channel Memristor 345
4.2 Small-Signal Equivalent Circuit and Nyquist Plot of the Sodium Ion-Channel Memristor 348
4.3 Small-Signal Equivalent Circuit and Nyquist Plot of the Hodgkin-Huxley Axon Circuit Model 351
5 Conclusion 358
References 358
12 Synapse as a Memristor 359
1 Introduction 359
2 How Do Neurons Work? 360
2.1 Synapse: Bridge for Neurons 361
2.2 Gerstner's Pair-Based STDP Model 361
3 Memristor Acting as a Synapse 362
3.1 Linares' Pair-Based Memristive STDP Model 363
3.2 Froemke's Triplet-Based STDP Model 365
3.3 Conflict with the Triplet Rule 366
4 Memristor Acting as a More Real Synapse 368
4.1 Memristive STDP Model with Adaptive Thresholds 368
4.2 Quantitative Equivalency of the Models 370
5 Short-Term Plasticity Revisited 373
References 374
13 Memristors and Memristive Devices for Neuromorphic Computing 376
1 Introduction 376
2 Mathematical Definition 377
2.1 Memristor - Strict Definition 377
2.2 Memristive Systems 378
3 Material Systems 378
3.1 Cation Migration 379
3.2 Anion Migration 380
3.3 Modeling 380
4 Synaptic Plasticity 383
4.1 Memristors as Weight Storage 384
4.2 Synapse Emulation 384
5 Hardware Topology 389
5.1 Crossbar Architecture 389
5.2 Hybrid Memristor/CMOS Circuitry 391
5.3 Emergent Behavior 391
6 Conclusion 393
References 394
14 Self-organization and Emergence of Dynamical Structures in Neuromorphic Atomic Switch Networks 397
1 Introduction 398
2 Emergence of a Complex Neuromorphic Architecture 400
2.1 Inorganic Synapses 401
2.2 The Growth of a Concept 403
2.3 Dynamical Circuits 406
3 Modelling and Simulation of Atomic Switches: From Nodes to Networks 408
4 Characterization of the Atomic Switch Network 410
4.1 Device Activation 410
4.2 Memristive Properties 412
4.3 Network Plasticity 414
4.4 Emergent Properties — Harmonic Generation 415
4.5 Emergent Properties — Criticality 416
5 Harnessing System Dynamics 419
5.1 Resistance Control 419
5.2 Reservoir Computing 421
6 Conclusions and Outlook 426
References 427
15 Spike-Timing-Dependent-Plasticity with Memristors 434
1 Introduction 435
2 STDP 436
2.1 STDP Versus Anti-STDP 439
2.2 Additive Versus Multiplicative STDP 439
3 Memristance 440
3.1 Memristor Moving-Wall Macro Model for Two-Terminal Devices 442
3.2 Memristor Filament Model for Two-Terminal Devices 443
4 Relation Between STDP and Memristance 445
4.1 Influence of Action Potential Shape 447
4.2 Wall Model Memristors Implement a Multiplicative Type of STDP 448
4.3 Filament Model Memristors Implement Additive STDP 449
5 Connecting Memristors with Spiking Neurons for Asynchronous STDP Learning 450
5.1 STDP Variations 454
6 Address Event Representation (AER) 455
7 Building a Self-learning Visual Cortex with Memristors and STDP-Ready AER Hardware 456
7.1 Topology of V1 Visual Cortex Layer and Physical Realization 457
7.2 AER Temporal Difference Retina 458
7.3 STDP Training Results of V1 Layer 459
8 Practical Limitations, Realistic Sizes, Pitches, Density, Crosstalk and Power Considerations 463
9 Conclusions 466
References 466
16 Designing Neuromorphic Computing Systems with Memristor Devices 473
1 Introduction 474
2 Preliminary 475
3 Hybrid Spiking-Based Multi-Layered Self-Learning Neuromorphic System Based on Memristor Crossbar Arrays 476
3.1 Problem and Motivation 476
3.2 Preliminary 477
3.3 Design Methodology and Hardware Implementation 479
3.4 System Evaluation 483
4 Hardware Implementation of Echo State Networks using Memristor Double Crossbar Arrays 485
4.1 Problem and Motivation 485
4.2 Preliminary 487
4.3 Proposed Architecture and Design Procedure 488
4.4 System Evaluation 492
5 Conclusions 496
References 496
17 Brain-Inspired Memristive Neural Networks for Unsupervised Learning 499
1 Introduction 499
2 RRAM Devices 501
3 RRAM Synapses 504
4 RRAM Networks 507
4.1 Feed-Forward Networks 507
4.2 Recurrent Neural Networks 516
5 Conclusions 522
References 522
18 Neuromorphic Devices and Networks Based on Memristors with Ionic Dynamics 530
1 Introduction 531
2 Ion Motion and Filament Dynamics in Oxide Memristors 532
2.1 Direct Visualization of Oxygen Ion Motion 533
2.2 Switching Dynamics in HfO2 Memristors 535
3 Device Optimizations on 2-Terminal Memristors for Neuromorphic Computing 538
3.1 Optimization of Weight Tuning Linearity 539
3.2 Correlation Between Number of Weight States with Oxide Structure 542
4 Development of Multi-terminal Synaptic Devices 544
4.1 Physically Evolving Networks Based on Self-organization of Ag Nanoclusters 544
4.2 3-Terminal Devices Emulating Heterosynaptic Plasticity 547
5 Neuromorphic Networks Based on Memristors 549
5.1 Neural Networks Composed of Heterosynaptic Devices with Flexible Learning Scheme 549
5.2 Tolerance of Intrinsic Device Variation in Fuzzy Restricted Boltzmann Machine Networks 552
6 Conclusion and Outlook 554
References 554
19 Associative Enhancement and Its Application in Memristor Based Neuromorphic Devices 558
1 Introduction 558
2 Flux and Continuum Resistance Memristors 560
3 Heterogeneous Pulse Stimuli Association, Synergy and Emergent Properties 564
4 Applications of Associative Memory in Neuromorphic Hardware 569
5 Summary 570
References 571
20 Organic Memristive Devices and Neuromorphic Circuits 574
1 Introduction 574
2 Architecture and Properties of Organic Memristive Devices 576
3 Logic Elements with Memory 580
4 Oscillating Element 582
5 Circuits with Adaptive and Neuromorphic Properties 584
6 Stochastic Fibrillar and Self-assembled Networks 587
7 Conclusion 594
References 595
21 Bio-inspired Neural Networks 597
1 Introduction 597
2 Biological Mechanisms 598
2.1 Connectome (Wires and Neurons) 598
2.2 Synapses (Resistance and Biochemistry) 599
2.3 Charge Propagation and Re-amplification (Ion Flux) 600
2.4 Two Protypes of Neurons: Excitatory (Glutamatergic) and Inhibitory (GABAergic) Neurons 602
2.5 Long-Term Potentiation 602
2.6 Long-Term Depression 604
2.7 Spike-Time-Dependent Plasticity 605
3 Implementations Using Memristive Systems and Conventional Electronics 607
3.1 (Leaky) Integrate and Fire Model 607
3.2 Long-Term Depression and Potentiation 608
3.3 Spike-Time-Dependent Plasticity 609
3.4 Pavlov's Dog 610
3.5 Hodgkin-Huxley Model 612
3.6 Complex Problem Solving Using Memristors 613
4 Conclusion and Outlook 615
References 616
22 Memristor Bridge-Based Artificial Neural Weighting Circuit 620
1 Introduction 620
2 Memristors and Memristive Devices 622
3 Synaptic Multiplication via Memristor Bridge 624
3.1 Weighting of Input Signals via the Memristor Bridge 625
4 Memristor-Bridge Neuron 626
5 Weight Programming in Memristor Bridge Synapses 627
6 Simulation 628
6.1 Linearity in Synaptic Weight Programming 629
6.2 Synaptic Weight (Multiplication) Processing 631
6.3 Applications 632
7 Conclusion 635
References 635
23 Cellular Nonlinear Networks with Memristor Synapses 637
1 Introduction 637
2 Brief Review of Memristor Models 640
2.1 Generalized BCM and Its Circuit Implementation 642
3 Memristor Synaptic Weighting Circuits for Neuromorphic Applications 644
3.1 Synaptic Weighting Circuit 647
3.2 Simulations 649
4 Conclusions 657
References 658
24 Evolving Memristive Neural Networks 661
1 Introduction 661
1.1 Content Overview 662
2 Background 662
2.1 Spiking Networks 663
2.2 Resistive Memory Synapses 663
2.3 Synaptic Plasticity 666
3 The System 668
3.1 Neural Control Architecture 668
3.2 Benchmark Synapses 670
3.3 STDP Implementation 672
4 Genetic Algorithm 674
4.1 Self-adaptive Mutation 675
4.2 Topology Mechanisms 675
4.3 GA Control of Variable Synapses 676
5 Experimentation 677
5.1 Test Environment 678
5.2 Results 679
6 Conclusions 687
References 688
25 Spiking Neural Computing in Memristive Neuromorphic Platforms 691
1 Introduction 691
2 Spiking Neural Networks 694
2.1 Spike Information Coding 695
2.2 Network Topology 696
3 Spiking Neuron Model 699
3.1 Biological, Artificial and Spiking Neuron 699
3.2 Spiking Neuron 701
4 Synapse and Learning 705
4.1 Synapse Model 707
4.2 Learning and Plasticity 709
5 Hardware Spiking Neural Network Systems 719
6 Discussion 722
6.1 Homeostasis 722
6.2 Winner-Take-All 723
7 Conclusion 724
References 724
26 Associative Networks and Perceptron Based on Memristors: Fundamentals and Algorithmic Implementation 729
1 Introduction 729
2 Crossbar Memory Arrays 731
3 Associative Memories 732
3.1 Willshaw Network 733
3.2 Hopfield Network 738
4 Perceptron 738
4.1 Principle of Operation 739
4.2 Algorithm Implementation 741
5 Conclusions 745
References 763
27 Spiking in Memristor Networks 766
1 Introduction 766
2 Single Memristor Spiking Properties 767
2.1 Properties of Memristor Spikes 767
2.2 A Mathematical Description of Experimentally-Measured Spikes 769
2.3 Theoretical Model of Single Spikes 772
2.4 The Memory-Conservation Theory as Applied to Memristor Spikes 775
2.5 Conservation Function 776
3 Constructionist Approach to Memristor Networks 777
3.1 Methodology 779
3.2 Two Memristor Circuit Results 782
3.3 Three Memristor Circuit Results 783
4 Conclusion 786
References 787
28 Three-Dimensional Crossbar Arrays of Self-rectifying Si/SiO2/Si Memristors 789
1 Introduction 789
2 Overview of Silicon Oxide Based Memristors 790
3 Self-rectifying P-Si/SiO2/N–Si Memristors 792
3.1 Unipolar Resistive Switching in Silicon Oxide 792
3.2 Room-Temperature Fabrication of Crystalline Silicon Electrode 793
3.3 Self-rectifying Resistive Switching Behavior 795
4 Switching Mechanism Study 798
4.1 Electrical Measurements 798
4.2 Physical Characterization 800
5 Three-Dimensional All Silicon Memristors Crossbars 802
5.1 SPICE Simulation 802
5.2 Experimental Measurements 806
6 Conclusions 809
References 810
29 The Self-directed Channel Memristor: Operational Dependence on the Metal-Chalcogenide Layer 812
1 Introduction 812
2 Materials Modifications 814
3 Device Structure and Fabrication 815
4 Electrical Measurements 818
4.1 DC I-V Measurements of All Samples at Room Temperature 818
4.2 CW I-V Room Temperature Results 823
4.3 LT Spice Model Simulations 825
4.4 DC and Cycling Endurance Measurements at Temperature 828
4.5 Programmed Resistance as a Function of Temperature 831
4.6 Endurance Cycling 833
5 Conclusions 835
References 838
30 Resistive Switching Devices: Mechanism, Performance and Integration 840
1 Resistive Switching Mechanisms 840
1.1 Electrochemical Metallization (ECM) 841
1.2 Valence Change Mechanism (VCM) 848
1.3 Thermochemical Mechanism (TCM) 856
1.4 Electrostatic/Electronic Effects 859
1.5 Phase Change Memory Mechanism (PCM) 862
2 Performance Improvement 864
2.1 Material Modulation 866
2.2 Device Structure Design 871
2.3 Operating Schemes Optimization 873
3 Integration of Resistive Switching Memory 877
3.1 Active Array 878
3.2 Passive Array 880
3.3 3D Architectures 889
3.4 Reliability Issue for 3D RRAM Array 893
References 899
31 Behavior of Multiple Memristor Circuits 909
1 Introduction 909
2 Single Memristor Circuit 911
2.1 Linear Model 912
2.2 Nonlinear Model 913
3 Transient and Stable State of Composite Memristance 914
4 Composite Memristance of Serially Connected Memristors 916
4.1 Serial Memristor Circuit with the Same Polarities 916
4.2 Serial Memristor Circuit with the Opposite Polarities 918
5 Composite Memristance of Parallel Memristors 919
5.1 Parallel Memristor Circuit with Identical Polarities 919
5.2 Parallel Memristor Circuit with Opposite Polarities 921
6 Simulation Results 922
6.1 Linear Model 922
6.2 Nonlinear Model 927
6.3 Memristance Variance 930
7 Conclusion 931
References 936
32 A Memristor-Based Chaotic System with Boundary Conditions 937
1 Introduction 937
2 The HP Memristor Model with Boundary Conditions 938
3 A New Memristive Chaotic System 942
4 Chaotic Attractor and its Bifurcation Analysis 945
5 Analog Implementation and SPICE Simulations of the Chaotic Attractor 946
6 Conclusions 949
References 950
33 Switching Synchronization and Metastable States in 1D Memristive Networks 951
1 Introduction 951
2 Accelerated and Decelerated Switching of Memristive Systems 955
3 Switching Synchronization 958
3.1 Numerical Results 958
3.2 Exact Analytical Solution 959
4 Metastable Memristive Lines 961
4.1 Numerical Results 963
4.2 Analytical Modeling 964
4.3 Application to Logic Gates 965
References 966
34 Modeling Memristor–Based Circuit Networks on Crossbar Architectures 968
1 Introduction 969
2 Application Potential of Memristor Based Circuits 970
3 Memristor Device Modeling 971
3.1 Related Work 971
3.2 A Novel Memristor Circuit Model 972
3.3 Verification of the Proposed Model 975
4 Dynamics of Memristors in Regular Network Connections 977
4.1 Memristors Connected in Series 981
4.2 Memristors Connected in Parallel 984
5 Circuit Design Paradigm 988
5.1 Implementation of the Universal Digital Logic Gates 988
5.2 Crossbar Circuit Simulator 991
5.3 Simulation of Memristor–Based Crossbar Circuits 992
5.4 Performance Evaluation of Memristor–Based Circuits 995
6 Conclusions 997
References 997
35 Memristive In Situ Computing 1000
1 Introduction 1001
1.1 Uncertainty Mitigation for Cycle-to-Cycle Switching 1002
2 Device Dynamics 1003
3 Analog In Situ Computing 1005
3.1 Muti-stable State 1005
3.2 Plasticity and Learning 1006
3.3 Programmable Analog Circuits 1007
4 Digital In Situ Computing 1008
4.1 Complementary Resistive Switch: Diodeless Nanocrossbars 1009
4.2 CRS-Based Boolean Operations 1009
References 1013
36 Memory Effects in Multi-terminal Solid State Devices and Their Applications 1016
1 Introduction 1016
2 Generalization of the Memristive Devices 1018
2.1 Resistive RAMs 1018
2.2 Mem-Capacitive Switching Devices 1022
2.3 Mem-Inductive Switching Devices 1023
2.4 Three-Terminal Memristive Devices 1024
2.5 Four-Terminal Memristive Devices 1029
3 Applications of Resistive RAMs 1033
3.1 Standalone Memories 1033
3.2 Generic Memory Structure (GMS) for Non-volatile FPGAs 1038
3.3 Resistive Programmable TSVs 1046
4 Applications of Multi-terminal Memristive Devices 1051
4.1 Neuromorphic Circuits 1051
4.2 Current and Temperature Sensor 1052
5 Conclusions 1056
References 1056
37 A Taxonomy and Evaluation Framework for Memristive Logic 1060
1 Introduction 1061
2 Classification of Memristive Logic Families 1062
2.1 Statefulness 1063
2.2 Proximity of Computation 1064
2.3 Flexibility 1065
3 Logic-Enabled Memory and Evaluation Metrics for Memristive Logic Families 1066
3.1 Logic-Enabled Memory 1066
3.2 Evaluation Metrics 1068
4 Latency of Memristive Logic Families 1069
4.1 In-Memory Logic Families 1070
4.2 Near-Memory Logic Families 1070
4.3 Out-of-Memory Logic Families 1071
5 Energy Efficiency of Memristive Logic Families 1071
5.1 Energy of In-Memory Logic Families 1072
5.2 Energy of Near-Memory Logic Families 1074
5.3 Energy of Out-of-Memory Logic Families 1075
6 Area Evaluation of Memristive Logic Families 1075
7 Case Study: Eight-Bit Full Adder Operation 1077
7.1 In-Memory Computing: MAGIC 1077
7.2 Near-Memory Computing: MAJ 1079
7.3 Out-of-Memory Computing: FBLC 1081
8 Evaluation of Eight-Bit Addition Case Study 1083
8.1 Methodology 1083
8.2 MAGIC 1084
8.3 MAJ 1085
8.4 FBLC 1086
8.5 Analysis of Results 1087
9 Single Instruction Multiple Data (SIMD) 1088
10 Conclusions 1091
References 1092
38 Memristive Stateful Logic 1095
1 Introduction 1095
2 Basic Memristive Stateful Logic Operations 1097
2.1 Generalized Stateful Logic 1099
2.2 Keeper Circuits 1100
2.3 Stateful Logic Operations 1102
2.4 Remarks 1104
3 Synthesis of Boolean Functions 1104
3.1 Definitions 1104
3.2 Synthesis Using the Conjunctive Normal Form 1105
3.3 Synthesis Without Complementary Representation of Variables 1107
3.4 Remarks 1108
4 Stateful Logic Within a Memristive Crossbar 1109
4.1 Preventing Sneak Current Paths 1109
4.2 Example on Stateful Logic Within a Memristive Crossbar 1112
5 Concluding Remarks 1113
References 1114
39 Memristor-Based Addition and Multiplication 1116
1 Introduction 1116
2 Previous Research 1117
2.1 Memristor Switch Logic 1117
2.2 Memristors as Analog Memory 1118
2.3 Memristor Interconnect Over CMOS 1119
3 Logic Operations Via Material Implication 1120
4 A Memristor Full Adder 1121
4.1 Full Adder Realized Via Material Implication 1122
5 A Memristor Ripple Carry Adder 1124
5.1 A Ripple Carry Adder Realized Via Material Implication 1125
6 A Memristor Carry Lookahead Adder 1126
7 A Memristor Array Multiplier 1127
8 Conclusions 1128
References 1129
40 Memristor Emulators 1130
1 Memristor Emulator Requirements 1130
2 Analog Emulators of the Memristor 1133
2.1 Mutator-Based Emulators 1133
2.2 Direct-Type Emulators 1137
3 Digital and Hybrid Emulators of Memristors 1140
4 Other Types of Memristor Emulators 1142
5 Future Possible Trends in Memristor Emulation 1143
6 Conclusions 1149
References 1150
41 Computing Shortest Paths in 2D and 3D Memristive Networks 1153
1 Introduction 1153
2 Methodology 1155
2.1 Memristive Components 1155
2.2 Memristive Fuse 1155
2.3 SPICE Simulations 1156
3 Shortest Path Solution of Mazes Using 2D Memristive Networks 1156
4 Multiple Shortest Path Computations Using 2D Memristive Networks 1160
5 Shortest Path Computations Using 3D Memristive Networks 1165
6 Conclusion 1167
References 1167
42 Computing Image and Motion with 3-D Memristive Grids 1169
1 Introduction 1170
2 Background 1172
2.1 Vertebrate's Retina: Architecture and Cells 1172
2.2 Mathematical Model of Memristors 1174
2.3 Optical Flow 1176
3 Biomimetic Outer Plexiform Layer 1177
3.1 Smoothing and Local Gaussian Filtering 1179
3.2 Edge Detection 1181
3.3 Adaptation to Light Conditions 1183
3.4 Fault Tolerance 1185
4 Detecting Moving Edges With Memristive Grids 1188
4.1 Simulation Methods 1188
4.2 Detection of Moving Edges Via Memristive State Thresholding 1189
4.3 Edge Detection Based on Monitoring the Memristance Modulation Rate 1190
4.4 Adaptation to Varying Lighting Conditions 1191
4.5 Memristance Variability Tolerance 1192
5 Double Layered Memristive Network 1192
5.1 Biomimetic OPL and IPL 1193
5.2 Emulating Transient Detection 1195
5.3 Directional and Speed Detection 1197
6 Conclusion 1198
References 1199
43 Solid-State Memcapacitors and Their Applications 1203
1 Introduction 1203
2 Physical Realizations of a Memcapacitor 1205
2.1 Capacitor with Elastic Membrane Electrode 1206
2.2 Capacitor with Multiple Metal and Insulator Layers 1207
2.3 Ferroelectric Capacitor 1207
2.4 Capacitor Appended with Memristive Layer 1208
3 Applications of Memcapacitors 1212
3.1 Device Models 1212
3.2 Memory 1212
3.3 Tunable Analog and Neuromorphic Circuits 1214
3.4 CNN Cell with Memcapacitors 1215
4 Conclusions 1218
References 1219
44 Reaction-Diffusion Media with Excitable Oregonators Coupled by Memristors 1221
1 Introduction 1221
2 The Model 1222
3 Dynamic Behaviors of Memristor RD model 1225
3.1 1-D Reaction-Diffusion Medium with Memristors 1225
3.2 2-D Reaction-Diffusion Medium with Memristors 1226
4 Conclusion 1230
References 1231
45 Mimicking Physarum Space Exploration with Networks of Memristive Oscillators 1232
1 Introduction 1233
1.1 Memristors in the Focus 1233
1.2 What Is So Special About Physarum polycephalum? 1234
1.3 Shortest Path and Maze Solving Physarum Computing 1234
2 Physarum-Inspired RLCM Oscillator 1237
2.1 Voltage-Controlled Behavioral Model of a Bipolar Memristor 1237
2.2 Circuit Dynamics and Training 1239
3 Memristive Circuit and System Applications 1241
3.1 Circuit-Level Approach 1242
3.2 System-Level Approach 1249
4 Conclusions 1261
References 1262
46 Autowaves in a Lattice of Memristor-Based Cells 1266
1 Introduction 1266
2 MCNN Model 1268
3 Simulation Results 1270
4 FPGA-Based Implementation of the MCNN 1271
References 1278
47 Memristor Cellular Automata and Memristor Discrete-Time Cellular Neural Networks 1279
1 Introduction 1279
2 Cellular Automata 1280
3 Cellular Neural Networks 1282
4 Memristor 1285
5 Memristor Cell 1287
5.1 Basic Cell 1287
5.2 Logical Operations 1288
5.3 Series Connection of Memristors 1295
5.4 Asynchronous Inputs 1297
6 Memristor Cellular Automaton 1301
6.1 Rule 126 Memristor Cellular Automaton 1303
6.2 Sierpinski Memristor Cellular Automaton 1306
6.3 Totalistic Two-Dimensional Memristor Cellular Automaton 1308
6.4 Horizontal Hole Detection Memristor Cellular Automaton 1310
6.5 Edge Detection Memristor Cellular Automaton 1312
6.6 Erosion 1313
6.7 Dilation 1315
6.8 Laplacian Memristor Cellular Automaton 1317
6.9 Sharpening Filter Memristor Cellular Automaton 1319
6.10 Noise Removal Memristor Cellular Automaton 1321
6.11 Inverse Half-Toning Memristor Cellular Automaton 1323
7 Memristor Cellular Automaton with Inputs 1324
8 Memristor Discrete-Time Cellular Neural Network 1327
8.1 Dilation 1330
8.2 Erosion 1330
8.3 Edge Detection 1332
8.4 Right Edge Detection 1333
8.5 Face-Vase Illusion 1334
8.6 Shadow Projection 1336
8.7 Line Detection 1337
8.8 Selected Objects Extraction 1337
8.9 Filled Contour Extraction 1337
8.10 Horizontal Hole and Vertical Hole Detection 1338
9 Advanced Memristor DTCNN 1340
9.1 Sandpile Cellular Automaton 1343
9.2 Game of Life 1345
9.3 Multitasking Capability 1347
10 Conclusion 1351
References 1351
Index 1352