Logarithmic Voltage-to-Time Converter for Analog-to-Digital Signal Conversion (eBook)

Mauro Santos (IEEE S'08-M'18) concluded his PhD from Instituto Superior Tecnico, Lisbon in 2018 in the area of microelectronics. His research interests are mainly in analog-to-digital signal conversion, analog and mixed signal IC design and power electronics.Jorge Manuel Guilherme is a professor at the Instituto Politecnico Tomar since 1996. He works at the Integrated Circuits Group of Instituto de Telecomunicações since 2004. His scientific interests are in the areas of microelectronics, data conversion and power management. Nuno Horta (S’89–M’97–SM’11) is an Associate Professor at IST Electrical and Computer Engineering Department. He is a Senior Researcher at Instituto de Telecomunicações, where he is the head of the Integrated Circuits Group. His research interests are mainly in analog and mixed-signal IC design, analog IC design automation, soft computing and data science.

Chapter 1        Introduction

1.1       Nonlinear Data Conversion

1.2       Motivation

1.3       Research Goals

1.4       Innovative Contributions

1.5       Achievements

1.6       Document Structure

Chapter 2        Nonlinear A/D Converters

2.1       Floating Point Converters

2.2       Logarithmic Converters

2.2.1    Logarithmic Pipeline Converters

2.2.2    Two-Step Logarithmic Converters

2.3       Piecewise Linear Converters

2.4       Oversampled Converters

2.4.1    Delta Converters

2.4.2    Sigma-Delta Converters

2.5       Nonlinear Conversion Using Pulse Width Modulation

2.5.1    Modified Integrating ADC

2.5.2    PWM Average Approximation

2.6       Nonlinear Conversion Using a Lookup Table

2.7       Other Architectures

2.8       Performance Metrics and Converter Testing

2.9       Conclusions

Chapter 3        Proposed Logarithmic ADC

3.1       Proposed Logarithmic ADC Architecture

3.2       Voltage-to-Time Conversion Element

3.3       Regeneration detection

3.4       Sources of nonlinearity

3.4.1    Offset

3.4.2    S3 switch resistance

3.4.3    Regeneration detection circuitry

3.4.4    Thermal Noise

3.5       Architecture Variants

3.5.1    Multiple Simultaneous Conversions

3.5.2    Polarity and magnitude independent conversion

3.6       Time-to-Digital Converter

3.7       Conclusions

Chapter 4        Logarithmic VTC Design

4.1       Determination of key design parameters

4.1.1    Sampling capacitors

4.1.2    Total transconductance

4.1.3    Degeneration resistors

4.1.4    Sampling switches

4.1.5    Regeneration detection

4.2       Simulaton Results

4.2.1    Process variations

4.2.2    Input referred noise and offset

4.3       Conclusions

Chapter 5        Circuit and Layout Level Validation

5.1       Configuration chain

5.2       Frequency divider

5.3       Frequency output pad

5.4       Voltage-to-time conversion elements

5.5       Phase generator

5.6       Programmable delay block

5.7       Common mode voltage effect on the regeneration detection voltage

5.8       Demonstrator integrated circuit layout

5.9       Simulation results

5.10     Conclusions

Chapter 6        Evaluation of the Prototype

6.1       Test Platform

6.2       Test Description

6.3       Experimental Results

6.3.1    Performance comparison

6.4       Input range limitation

6.5       Conclusions

Chapter 7        Future Work and Conclusions

7.1       Conclusions

7.2       Future Work

7.2.1    Calibration

7.2.2    Improved Conversion Method

References