Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems (eBook)

Prof. Xinpeng Xing received his Bachelor and Master degrees both in Electronics Engineering from Beijing University of Aeronautics and Astronautics and Tsinghua University respectively. In October 2013, He is granted with PhD degree in engineering in KU Leuven, his doctor thesis is about design of high-bandwidth low-power Delta-Sigma Modulators. Now he is an assistant professor at Graduate School at Shenzhen, Tsinghua University, and his research interest is analog, mixed-mode, RF integrated circuits design.Georges G.E. Gielen Has been a  Full Professor at Katholieke Universiteit Leuven since 2000 and, since August 2012, has served as Chair of the Department of Electrical Engineering. He is also the Chair of the Leuven ICT research center, and the PI coordinator of the Leuven CHIPS Center of Excellence.His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation (modeling, simulation and symbolic analysis, analog synthesis, analog layout generation, analog and mixed-signal testing). He is coordinator or partner of several (industrial) research projects in this areas. He has authored or coauthored 7 books and more than 450 papers in edited books, international journals and conference proceedings. He is regularly a member of the Program Committees of international conferences, having served as General Chair of the DATE conference in 2006 and of the ICCAD conference in 2007. He serves regularly as member of editorial boards of international journals (IEEE Transactions on Circuits and Systems, IEEE Transactions on Computer-Aided Design, Springer International Journal on Analog Integrated Circuits and Signal Processing, Elsevier Integration). He received the 1995 Best Paper Award in the John Wiley international journal on Circuit Theory and Applications, and was the 1997 Laureate of the Belgian Royal Academy on Sciences, Literature and Arts in the discipline of Engineering. He received the 2000 Alcatel Award from the Belgian National Fund of Scientific Research for his innovative research in telecommunications, and won the DATE 2004 conference Best Paper Award. He served as appointed member of the Board of Governors of the IEEE Council on Electronic Design Automation, and as Chairman of the IEEE Benelux CAS Chapter. He served as the President of the IEEE Circuits and Systems Society in 2005, and as Chair of the IEEE Benelux Section in 2009-2011. He is the Chair of EDAA. He was elected DATE Fellow in 2007, and received the IEEE Computer Society Outstanding Contribution Award and the IEEE Circuits and Systems Society Meritorious Service Award in 2007. He is a Fellow of the IEEE.

Preface 7
Acknowledgements 9
Contents 10
Abbreviations 14
List of Figures 18
List of Tables 25
1 Introduction 26
1.1 Background and Motivation 26
1.1.1 Communication Evolution 26
1.1.2 CMOS Technology 28
1.1.3 Wireless Receiver Architectures 31
1.2 The Research Objective of the Book 33
1.3 The Book Organization 34
References 35
2 A/D Converters and Applications 37
2.1 Introduction 37
2.2 ADC Specifications 38
2.2.1 ADC Speed 38
2.2.2 ADC Accuracy 38
2.2.3 ADC FoM 40
2.3 ADC Architectures 40
2.3.1 Flash ADC 43
2.3.2 Two-Step ADC 45
2.3.3 Pipelined ADC 46
2.3.4 SAR ADC 47
2.3.5 Delta-Sigma ADC 48
2.3.6 ADC Architecture Summmary and Comparison 50
2.4 Application of ADC in Communications 52
2.5 Conclusions 57
References 58
3 Continuous-Time Delta-Sigma Modulators 60
3.1 Introduction 60
3.2 DSM Basics: Oversampling and Noise-Shaping 61
3.3 DSM Structures 64
3.3.1 Discrete-Time and Continuous-Time DSMs 64
3.3.2 1st-Order and Higher-Order DSMs 67
3.3.3 Single-Loop and MASH DSMs 68
3.3.4 The ??-0 and 0-?? MASH Structures 69
3.3.5 Single-Bit and Multi-bit DSMs 71
3.3.6 Feedforward, Feedback and Hybrid DSMs 73
3.3.7 Resonator 75
3.3.8 Feedin Paths 76
3.4 CT DSM Nonidealities and Modeling 76
3.4.1 Loop Filter Nonidealities and Modeling 77
3.4.2 DAC Nonidealities and Modelling 82
3.4.3 Quantizer Nonidealities and Modeling 86
3.5 Conclusions 87
References 88
4 VCO-Based ADCs 90
4.1 Introduction 90
4.2 VCO-Based Quantizers 91
4.2.1 Single-Phase Counting VCO-Based Quantizer 91
4.2.2 Multi-phase Counting VCO-Based Quantizer 91
4.2.3 Frequency-Type VCO-Based Quantizer 92
4.2.4 Phase-Type VCO-Based Quantizer 95
4.3 Closed-Loop VCO-Based DSMs 95
4.3.1 DSM with Frequency-Type VCO-Based Quantizer 96
4.3.2 DSM with Phase-Type VCO-Based Quantizer 97
4.3.3 DSM with Residual-Cancelling VCO-Based Quantizer 97
4.4 Open-Loop VCO-Based ADCs 99
4.4.1 VCO-Based ADC with Background Digital Calibration 99
4.4.2 VCO-Based ADC with Counting and Foreground Digital Calibration 100
4.4.3 VCO-Based ADC with PWM Precoding 101
4.5 Conclusions 103
References 103
5 CT DSM ADCs with VCO-Based Quantization 105
5.1 Introduction 105
5.2 A 40MHz-BW 12-Bit CT DSM with Digital Calibration and Shaped SC DAC 106
5.2.1 Structure of the CT DSM 106
5.2.2 Delta-Sigma Modulator Building Blocks Design 111
5.2.3 Measurement Setup and Experimental Results 117
5.3 A 40MHz-BW 12-Bit CT DSM with Capacitive Local Feedback and Current-Sharing OTA 119
5.3.1 System Design of the 40MHz 12-Bit CT DSM 121
5.3.2 Circuit Design of the DSM Building Blocks 123
5.3.3 Measurement Results and Discussions 126
5.4 Conclusions 128
References 129
6 Two-Step Open-Loop VCO-Based ADC 131
6.1 Introduction 131
6.2 Architecture Design of Two-Step Open-Loop VCO-Based ADC 132
6.2.1 A Two-Step Open-Loop VCO-Based ADC Architecture 132
6.2.2 Nonidealities of the Two-Step Open-Loop VCO-Based ADC 135
6.3 Circuit Implementation of the Two-Step Open-Loop VCO-Based ADC 138
6.3.1 VCO-Based Quantizer Design 139
6.3.2 DAC and Subtractor Design 141
6.4 Experimental Results and Discussions 144
6.5 Conclusions 146
References 147
7 VCO-Based 0-?? MASH ADC 148
7.1 Introduction 148
7.2 Architecture Analysis of the 0-?? MASH VCO-Based ADC 149
7.2.1 0-?? MASH VCO-Based ADC 149
7.2.2 Nonlinearity-Cancellation Robustness Against PVT Variations 152
7.2.3 System Architecture of a 0--2 MASH VCO-Based ?? ADC 153
7.2.4 Delay Matching Technique 155
7.3 Circuit Implementation of the 0--2 MASH VCO-Based ?? ADC 157
7.3.1 Three-Input Adder 157
7.3.2 VCO-Based Quantizer 158
7.3.3 Integrator 160
7.3.4 DACs 162
7.3.5 Interface 163
7.4 Experimental Results 164
7.5 Conclusions 171
References 171
8 Fully-VCO-Based High-Order ?? ADC 173
8.1 Introduction 173
8.2 Integrators 173
8.2.1 Traditional Analog Integrator 173
8.2.2 VCO-Based Integrator 175
8.2.3 Fully-VCO-Based ?? ADC Structure 177
8.3 Design Example: A Fully-VCO-Based 0-2 MASH VCO-Based ?? ADC 178
8.3.1 System Architecture 178
8.3.2 Circuit Implementation 180
8.3.3 Experimental Results 183
8.4 Conclusions 191
References 191
9 Conclusions 192
9.1 Summary and Conclusions 192
9.2 Suggestions for Future Work 194
References 197
Index 198