Hardware IP Security and Trust (eBook)

Prabhat Mishra is an Associate Professor in the Department of Computer and Information Science and Engineering (CISE) at the University of Florida (UF) where he leads the CISE Embedded Systems Lab. His research interests include design automation of embedded systems, energy-aware computing, reconfigurable architectures, hardware security and trust, system validation and verification, and post-silicon debug. He received his B.E. from Jadavpur University, Kolkata in 1994, M.Tech. from the Indian Institute of Technology, Kharagpur in 1996, and Ph.D. from the University of California, Irvine in 2004 -- all in Computer Science and Engineering. Prior to joining University of Florida, he spent several years in various companies including Intel, Motorola, Synopsys and Texas Instruments. He has published four books and more than 100 research articles in premier international journals and conferences. His research has been recognized by several awards including the NSF CAREER Award from the National Science Foundation, IBM Faculty Award, two best paper awards (VLSI Design 2011 and CODES+ISSS 2003), five best paper nominations (including DAC'09 and DATE'12), and 2004 EDAA Outstanding Dissertation Award from the European Design Automation Association. He has also received the 2007 International Educator of the Year Award from the UF College of Engineering for his international research and teaching contributions. Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is a professor in the department of Electrical and Computer Engineering at University of Florida, Gainesville, FL, USA. Earlier, Dr. Bhunia has served as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over ten years of research and development experience with over 200 publications in peer-reviewed journals and premier conferences and four books (three edited) in the area of VLSI design, CAD and test techniques. His research interests include low power and robust design, hardware security and trust, adaptive nanocomputing and novel test methodologies. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. Dr. Bhunia received IBM Faculty Award (2013), National Science Foundation (NSF) career development award (2011), Semiconductor Research Corporation (SRC) technical excellence award (2005), best paper award in International Conference on VLSI Design (VLSI Design 2012), best paper award in International Conference on Computer Design (ICCD 2004), best paper award in Latin American Test Workshop (LATW 2003), and best paper nomination in Asia and South Pacific Design Automation Conference (ASP-DAC 2006) and in Hardware Oriented Test and Security (HOST 2010), nomination for John S. Diekhoff Award, Case Western Reserve University (2010) and SRC Inventor Recognition Award (2009). Mark M. Tehranipoor is currently the Intel Charles E. Young Professor in Cybersecurity at the Department of Electrical and Computer Engineering, the University of Florida. His current research projects include: hardware security and trust, electronics supply chain security, counterfeit IC detection and prevention, and reliable and testable VLSI design. Prof. Tehranipoor has published over 250 journal articles and refereed conference papers and has given more than 150 invited talks and keynote addresses since 2006. In addition, he has published six books and ten book chapters. His projects are sponsored by both the industry (Semiconductor Research Corporation (SRC), Texas Instruments, Freescale, Comcast, Honeywell, LSI, Mentor Graphics, Juniper, R3Logic, Cisco, Qualcomm, MediaTeck, etc.) and the Government (NSF, ARO, MDA, DOD, AFOSR, DOE, etc.). Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut. Prof. Tehranipoor is a Senior Member of the IEEE, Golden Core Member of IEEE Computer Society, and Member of ACM and ACM SIGDA. He is also a member of Connecticut Academy of Science and Engineering (CASE).

Acknowledgements 5
Contents 7
Abbreviations (Acronyms) 9
Part I Introduction 13
1 Security and Trust Vulnerabilities in Third-Party IPs 14
1.1 Introduction 14
1.2 Design and Validation of SoCs 16
1.3 Security and Trust Vulnerabilities in Third-Party IPs 17
1.4 Trustworthy SoC Design Using Untrusted IPs 20
1.5 Book Organization 23
References 24
Part II Trust Analysis 26
2 Security Rule Check 27
2.1 Introduction 27
2.2 Security Assets and Attack Models 29
2.2.1 Asset 29
2.2.2 Potential Access to Assets 31
2.2.3 Potential Adversary for Intentional Attacks 32
2.3 DSeRC: Design Security Rule Check 33
2.3.1 Vulnerabilities 35
2.3.1.1 Sources of Vulnerabilities 35
2.3.1.2 Vulnerabilities at Different Abstraction Levels 38
2.3.2 Metrics and Rules 39
2.3.3 Workflow of DSeRC Framework 42
2.4 Development of DSeRC Framework 43
2.4.1 Vulnerabilities, Metrics, and Rules 43
2.4.2 Tool Development 44
2.4.3 Development of Design Guidelines for Security 44
2.4.4 Development of Countermeasure Techniques 44
2.5 Conclusion 45
References 45
3 Digital Circuit Vulnerabilities to Hardware Trojans 47
3.1 Introduction 47
3.2 The Gate-Level Design Vulnerability Analysis Flow 48
3.3 The Layout-Level Design Vulnerability Analysis Flow 50
3.3.1 Cell and Routing Analyses 50
3.3.2 Net Analysis 52
3.4 Trojan Analyses 56
3.5 Conclusions 60
References 60
4 Code Coverage Analysis for IP Trust Verification 62
4.1 Introduction 62
4.2 SoC Design Flow 63
4.3 Hardware Trojan Structure 65
4.4 Related Work 65
4.5 A Case Study for IP Trust Verification 68
4.5.1 Formal Verification and Coverage Analysis 69
4.5.2 Techniques for Suspicious Signals Reduction 71
4.5.2.1 Phase 1: Test Bench Generation and Suspicious Signal Identification 71
4.5.2.2 Phase 2: Suspicious Signals Analysis 72
4.6 Simulation Results 74
4.6.1 Benchmark Setup 74
4.6.2 Impact of Test Bench on Coverage Analysis 75
4.6.3 Reducing the Suspicious Signals 76
4.6.4 Trojan Coverage Analysis 78
4.7 Conclusion 79
References 79
5 Analyzing Circuit Layout to Probing Attack 82
5.1 Introduction 82
5.2 Microprobing Attack Techniques 85
5.2.1 Essential Steps in a Probing Attack 85
5.2.2 Microprobing Through Milling 86
5.2.3 Back-Side Techniques 87
5.2.4 Other Related Techniques 88
5.3 Protection Against Probing Attacks 89
5.3.1 Active Shields 89
5.3.2 Techniques to Attack and Secure Active Shields 90
5.3.2.1 Routing Overhead 90
5.3.2.2 Stuck on Top Metal Layer 91
5.3.3 Other Antiprobing Designs 93
5.3.4 Summary on Antiprobing Protections 94
5.4 Layout-Based Evaluation Framework 94
5.4.1 Motivation 94
5.4.2 Assessment Rules 95
5.4.3 State-of-the-Art Active Shield Model 97
5.4.4 Impact of Milling Angle upon Effect of Bypass Attack 99
5.4.5 Algorithm to Find Exposed Area 100
5.4.6 Discussions on Applications of Exposed Area Algorithm 104
5.5 Conclusion 104
References 105
6 Testing of Side-Channel Leakage of Cryptographic Intellectual Properties: Metrics and Evaluations 108
6.1 Introduction 108
6.2 Preliminaries on Statistical Testing and Testing of Hypothesis 110
6.2.1 Sampling and Estimation 111
6.2.2 Some Statistical Distributions 112
6.2.3 Estimation and Test of Significance 112
6.2.4 Test of Significance: Statistical Hypothesis Testing 113
6.3 Formalizing SCA and the Success Rate of Side-Channel Adversary: Guessing Entropy 115
6.3.1 Success Rate of a Side-Channel Adversary 115
6.3.2 Guessing Entropy of an Adversary 117
6.4 Leakage Detection in SCA Traces: NICV and SNR 117
6.4.1 Normalized Inter-Class Variance 118
6.4.2 NICV and SNR 120
6.4.3 Related Work in Leakage Detection 121
6.4.4 Case Study: Application on AES 121
6.5 Test Vector Leakage Assessment Methodology 123
6.6 Equivalence of NICV and TVLA 125
6.7 TVLA on Higher Order Side-Channel Attacks 127
6.7.1 Estimation of Mean 128
6.7.2 Estimation of Variance 130
6.8 Case Study: Private Circuit 131
6.8.1 Experimental Analysis and Result 132
6.8.1.1 Optimized SIMON 132
6.8.1.2 2-Input LUT Based SIMON 134
6.8.1.3 Synchronized 2-Input LUT Based SIMON 135
6.9 Conclusion 138
References 138
Part III Effective Countermeasures 141
7 Hardware Hardening Approaches Using Camouflaging, Encryption, and Obfuscation 142
7.1 Introduction 142
7.2 Terminology 144
7.3 State of the Art 144
7.3.1 Camouflaging 144
7.3.2 Logic Encryption 146
7.3.2.1 Attacks Against Logic Encryption 147
7.3.2.2 Logic Encryption Algorithms 148
7.3.3 State Obfuscation 149
7.4 Dynamic State-Deflection-Based Obfuscation Method 150
7.4.1 Overview of DSD Obfuscation 150
7.4.2 Black Hole State Creation for Gate-level Obfuscation 152
7.4.3 Dynamic Transition in Black Hole Cluster 153
7.4.4 Experimental Results 153
7.4.4.1 Experimental Setup 153
7.4.4.2 Hardening Capability Against Circuit Switching Activity Analysis Attack 154
7.4.4.3 Number of Unique State Register Patterns in Obfuscation Mode 157
7.4.4.4 Area and Power Overhead 158
7.4.5 Discussion 159
7.5 Obfuscation for Three-Dimensional ICs 159
7.5.1 Leveraging 3D for Security 159
7.5.2 Trustworthiness of Vertical Communication 160
7.5.3 Proposed Obfuscation Method for 3D ICs 161
7.5.3.1 Overview of Proposed 3D Obfuscation Method 161
7.5.3.2 Proposed 3D Router Design 163
7.5.3.3 Assessment on 3D Obfuscation Method 165
7.5.4 Discussion 167
7.6 Summary 167
References 167
8 A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Side-Channel Attacks 171
8.1 Introduction 171
8.2 Mutating Runtime Architecture 173
8.2.1 Design Properties 173
8.2.2 Online Allocation Method 174
8.2.3 DynamicBinding Method 176
8.2.4 FlexibleScheduling Method 178
8.3 Design Flow 180
8.4 Case Study: Block Cipher AES 128-Bit 181
8.4.1 Partitioning of the AES Modules 182
8.4.2 Implementation 183
8.4.2.1 Design Requirements 183
8.4.2.2 Data Path Architecture 184
8.4.2.3 Virtualization Scheme 186
8.4.2.4 Merging Round and Routines 186
8.4.3 Side-Channel Analysis Results 187
8.5 Summary 188
References 189
Part IV Security and Trust Validation 191
9 Validation of IP Security and Trust 192
9.1 Introduction 192
9.2 Logic Testing for Trojan Detection 193
9.2.1 Utilization Rarely Used Components for Trojan Detection 194
9.2.2 ATPG-Based Test Generation for Trojan Detection 195
9.3 Trojan Detection Using Equivalence Checking 196
9.3.1 Gröbner Basis Theory for Equivalence Checking of Arithmetic Circuits 197
9.3.2 Automated Debugging of Functional Trojans Using Remainders 201
9.3.2.1 Test Generation for Trojan Detection 203
9.3.2.2 Trojan Localization 204
9.4 Trojan Detection Using Model Checking 206
References 208
10 IP Trust Validation Using Proof-Carrying Hardware 211
10.1 Introduction 211
10.2 Overview of Formal Verification Methods for IP Protection 212
10.2.1 Threat Model 213
10.2.2 Formal Verification Methods 213
10.2.2.1 Theorem Prover 214
10.2.2.2 Model Checker 214
10.3 Proof-Carrying Hardware Framework for IP Protection 215
10.3.1 Semantic Translation 217
10.3.2 Data Protection Through Information Flow Tracking 219
10.3.2.1 Static Information Flow Tracking Scheme 220
10.3.2.2 Dynamic Information Assurance Scheme 221
10.3.3 Hierarchy Preserving Verification 222
10.3.4 Integrating Theorem Prover and Model Checker 224
10.4 Conclusion 226
References 226
11 Hardware Trust Verification 230
11.1 Introduction 230
11.2 HT Classification 231
11.2.1 Bug-Based HT 231
11.2.2 Parasite-Based HT 232
11.3 Verification Techniques for Hardware Trust 233
11.3.1 Functional Verification 233
11.3.2 Formal Verification 233
11.3.3 Trust Verification 233
11.3.3.1 Unused Circuit Identification 234
11.3.3.2 VeriTrust 235
11.3.3.3 FANCI 240
11.3.3.4 Discussion 242
11.4 Stealthy HT Designs Defeating Trust Verification 243
11.4.1 HTs Evade UCI 243
11.4.1.1 Motivational Case 243
11.4.2 HT Design Against UCI 244
11.4.3 HTs Evade VeriTrust 246
11.4.3.1 Motivational Case 246
11.4.3.2 HT Design Against VeriTrust 248
11.4.4 HTs Evade FANCI 250
11.4.4.1 Motivational Case 250
11.4.5 HT Design Against FANCI 252
11.4.6 Discussion 255
References 255
12 Verification and Trust for Unspecified IP Functionality 257
12.1 Introduction 257
12.1.1 Unspecified IP Functionality 257
12.1.2 Hardware Trojans 258
12.2 Trojans in RTL Don't Cares 261
12.2.1 Illustrative Examples 262
12.2.2 Automated Identification of Dangerous Don't Cares 265
12.2.3 Elliptic Curve Processor Case Study 267
12.2.3.1 The Hardware Trojan 267
12.2.3.2 Automated X-Analysis 268
12.3 Identifying Dangerous Unspecified Functionality 270
12.3.1 Background: Mutation Testing and Coverage Discounting 270
12.3.2 Identification Procedure 272
12.3.3 UART Communication Controller Case Study 274
12.3.3.1 The Wishbone Bus Trojan 275
12.3.3.2 Interrupt Output Signal Checker Bug 276
12.4 Trojans in Partially Specified On-chip Bus Functionality 277
12.4.1 Threat Model 278
12.4.2 Trojan Communication Channel 278
12.4.2.1 Topology Dependent Trojan Channel Properties 280
12.4.2.2 Protocol Dependent Trojan Channel Properties 280
12.4.3 AXI4-Lite Interconnect Trojan Example 281
12.4.3.1 Overhead 284
12.5 Conclusion 285
References 285
13 Verifying Security Properties in Modern SoCs Using Instruction-Level Abstractions 288
13.1 Introduction 288
13.1.1 Challenges in SoC Security Verification 289
13.1.1.1 Need for Hardware/Firmware Co-verification 290
13.1.1.2 SoC Verification Through Abstraction 290
13.1.1.3 Challenges in Specifying Security Properties 291
13.1.2 SoC Security Verification Using Instruction-Level Abstractions 292
13.1.2.1 ILA Synthesis and Verification 292
13.1.2.2 Security Verification Using the ILA 293
13.1.2.3 Summarizing ILA-Based Verification 293
13.2 Instruction-Level Abstractions 294
13.2.1 ILA Overview 294
13.2.2 ILA Definition 295
13.2.2.1 Notation 295
13.2.2.2 Architectural State and Inputs 295
13.2.2.3 Fetching an Instruction 296
13.2.2.4 Decoding an Instruction 296
13.2.2.5 Executing an Instruction 297
13.2.2.6 Syntax 297
13.2.2.7 Putting It All Together 298
13.2.3 ILA Synthesis 299
13.2.3.1 Notation and Problem Statement 299
13.2.3.2 Template Language 299
13.2.3.3 An Illustrative Example 300
13.2.3.4 Synthesis Algorithm 301
13.2.4 ILA Verification 302
13.2.4.1 Verifying Abstraction Correctness 303
13.2.4.2 Discussion of Verification Issues 303
13.2.4.3 Verification Correctness 304
13.2.5 Practical Case Study 304
13.2.5.1 Methodology 305
13.2.5.2 Example SoC Structure 305
13.2.5.3 Summary of Synthesis Results 305
13.2.5.4 Typical ILAs 306
13.2.5.5 Summary of Verification Results 307
13.3 Security Verification Using ILAs 309
13.3.1 System and Threat Model Overview 310
13.3.1.1 System-On-Chip Model 310
13.3.1.2 Threat Model 310
13.3.1.3 Security Objectives 310
13.3.1.4 Modelling the Attacker 311
13.3.2 Specifying Information Flow Properties 311
13.3.3 Firmware Execution Model 312
13.3.3.1 Execution State 312
13.3.3.2 A Review of Symbolic Execution 312
13.3.4 Verifying Information Flow Properties 315
13.3.5 Evaluation 318
13.3.5.1 Methodology 318
13.3.5.2 Security Objectives 318
13.3.5.3 Summary of Verification Results 319
13.4 Discussion and Related Work 319
13.4.1 SoC Security Verification 319
13.4.2 Related Work 320
13.4.2.1 Synthesizing Abstractions 320
13.4.2.2 SoC Verification 320
13.4.2.3 Symbolic Execution and Taint Analysis 321
13.5 Conclusion 321
References 321
14 Test Generation for Detection of Malicious Parametric Variations 325
14.1 Introduction 325
14.2 Power Virus for Gate-Level IPs 326
14.2.1 Pseudo-Boolean Satisfiability Approach 327
14.2.2 Largest Fanout First Approach 328
14.2.3 Cost-Benefit Analysis Approach 329
14.2.4 Power Virus for Sequential Circuits 330
14.3 Power Virus for Processor IPs 331
14.3.1 Stress Benchmarks 331
14.3.2 Power Virus Generation for Single-Core IPs 332
14.3.2.1 Exploration Space of Program Characteristics 333
14.3.2.2 Code Generation 334
14.3.3 Power Virus for Multi-Core IPs 335
14.3.3.1 Space Exploration of Program Characteristics 335
14.3.3.2 Multi-Threaded Power Virus Generation 336
14.4 Temperature Virus 336
14.4.1 Temperature Virus for Gate-Level IPs 336
14.4.2 Temperature Virus for Processor IPs 338
14.5 Conclusion 339
References 339
Part V Conclusion 341
15 The Future of Trustworthy SoC Design 342
15.1 Summary 342
15.1.1 Trust Vulnerability Analysis 342
15.1.2 Effective Countermeasures 343
15.1.3 Security and Trust Validation 343
15.2 Future Directions 344
15.2.1 Security and Trust Verification for Encrypted IPs 344
15.2.2 Security and Trust Verification for Obfuscated IPs 345
15.2.3 Security and Trust Verification for Hard IPs 345
15.2.4 Security and Trust Verification During SoC Design Flow 346
15.2.5 Unintentional Vulnerabilities 346
15.2.6 Multi-Security Objectives Design 347
15.2.7 Metrics and Benchmarks 347
References 348
Index 349