Cache and Interconnect Architectures in Multiprocessors
Springer-Verlag New York Inc.
978-1-4612-8824-4 (ISBN)
TLB Consistency and Virtual Caches.- The Cost of TLB Consistency.- Virtual-Address Caches in Multiprocessors.- Simulation and Performance Studies — Cache Coherence.- A Critique of Trace-Driven Simulation for Shared-Memory Multiprocessors.- Performance of Symmetry Multiprocessor System.- Analysis of Cache Invalidation Patterns in Shared-Memory Multiprocessors.- Memory-Access Penalties in Write-Invalidate Cache Coherence Protocols.- Performance of Parallel Loops using Alternate Cache Consistency Protocols on a Non-Bus Multiprocessor.- Predicting the Performance of Shared Multiprocessor Caches.- Cache Coherence Protocols.- The Cache Coherence Protocol of the Data Diffusion Machine.- SCI (Scalable Coherent Interface) Cache Coherence.- Interconnect Architectures.- Performance Evaluation of Wide Shared Bus Multiprocessors.- Crossbar-Multi-processor Architecture.- “CHESS” Multiprocessor—A Processor-Memory Grid for Parallel Programming.- Software Cache Coherence Schemes.- Software-directed Cache Management in Multiprocessors.
Zusatzinfo | XIV, 277 p. |
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Verlagsort | New York, NY |
Sprache | englisch |
Maße | 155 x 235 mm |
Themenwelt | Mathematik / Informatik ► Informatik ► Datenbanken |
Mathematik / Informatik ► Informatik ► Theorie / Studium | |
Technik ► Elektrotechnik / Energietechnik | |
ISBN-10 | 1-4612-8824-X / 146128824X |
ISBN-13 | 978-1-4612-8824-4 / 9781461288244 |
Zustand | Neuware |
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