Robust Computing with Nano-scale Devices (eBook)

Contents 6
Introduction 10
Fault Tolerant Nanocomputing 15
Introduction 15
Principles of Fault Tolerant Nanocomputer Systems 17
Hardware Redundancy 19
N-Modular Redundancy 19
NAND Multiplexing 21
Reconfiguration 23
Information Redundancy 26
Time Redundancy 26
Coverage 27
Process Variations in Nanoscale Circuits 28
Fault Tolerant Nanocomputer Applications 29
General-Purpose Computing 30
Long-Life Applications 30
Critical-Computation Applications 30
High-Availability Applications 31
Maintenance Postponement Applications 31
Trends and Future 31
References 32
Transistor-Level Based Defect-Tolerance for Reliable Nanoelectronics 36
Introduction 36
Previous Approaches 38
Defect-Tolerant Techniques 38
Defect Avoidance Techniques 40
Defect-Tolerant FPGA Design Techniques 42
Reliability Analysis 44
Proposed Defect Tolerance Technique 44
Experimental Results 49
Stuck-Open and Stuck-Short Defect Analysis 49
Bridging Defect Analysis 52
Conclusion 53
References 54
Fault-Tolerant Design for Nanowire-Based Programmable Logic Arrays 57
Introduction 57
Background 58
Nanowire-Based PLA 58
Defect Model 59
Redundancy-Based Defect-Tolerant Techniques 60
Conventional Redundancy-Based Techniques 60
Logic Duplication in PLA 61
Defect-Aware Logic Mapping for Nanowire-Based PLA 62
Defect-Free Subset Identification 63
Defect-Aware Mapping Through Bipartite Graph Embedding 64
SAT-Based Defect-Aware Mapping 66
Experimental Results 70
Conclusions and Perspectives 73
References 73
Built-In Self-Test and Defect Tolerance for Molecular Electronics-Based NanoFabrics 75
Introduction 75
NanoFabric Architecture 76
Fault Model 78
Summary of the Proposed Method 79
Related Prior Work 79
BIST Procedure 81
Test Architectures (TAs) 82
Test Procedure 84
Test Configurations 85
Test Configurations for Detecting Faults in NanoBlocks 85
Test Configurations for Detecting Faults in SwitchBlocks 88
Number of Test Configurations 91
Time Analysis for BIST 93
Recovery Analysis 94
Simulation and Results 96
Discussion 101
Conclusion 102
References 102
The Prospect and Challenges of CNFET Based Circuits: A Physical Insight 105
Introduction 105
Fundamentals of CNFET 107
Compact Model of CNFET 109
Impact of Parasitics on Circuit Performance 113
Geometry Dependent Parasitic Capacitance 114
Analysis of Fringe Capacitance 115
Impact of Process Variation 118
A Physical Insight to CNFET Characteristics Under Process Variation 118
CNFET Performance Under Process Variation 119
Impact on Drive Current 121
Impact on Capacitance 123
Impact on Circuit Performance 123
Summary 125
Appendix I: Polynomial Expression of QCNT 126
References 127
Computing with Nanowires: A Self Assembled Neuromorphic Architecture 130
Introduction 130
Self Assembly of Neuromorphic Networks 131
Electrical Characterization of the Nanowires 132
What Causes the Negative Differential Resistance? 135
Other Electrical Parameters 135
Simulation Results 137
Conclusion 141
References 141
Computational Opportunities and CAD for Nanotechnologies 142
Introduction 142
A Holistic CAD Platform for Nanotechnologies 144
High-Level Modeling and Simulation Tool (HLMS) 146
Artificial Ecosystems 149
Spontaneous Creation of Artificial Organisms 149
Optimization of Existing Functions 150
Acquisition of New Functions 150
Systems of Particles and Emergence of Relativistic Space-Time 151
Nano-Network Architecture Fit Tool (NAF) 152
Circuit Synthesis Tool (CS) 153
Architectures for Complex Systems Implementation 154
Architectures for Systems Comporting Mobile Modules 154
Generic Communication Architectures for Systems Comprising Mobile Modules 158
Associative Computer Approach 158
Nonconventional Architectures 162
Computational Model of Quantum Systems 162
Implementing Complex Systems Composed of Quantum Objects 166
Quantum Computing 167
CAD for Non-conventional Architectures 174
Conclusions 175
References 176
Index 179