System and Architecture (eBook)

Prof. Sunil Kumar Muttoo is working as a Professor and Head of the Department of Computer Science, University of Delhi. He completed his M.Sc., M.Phil., Ph.D. at the University of Delhi and his M.Tech. (Computer Science and Data Processing, CSDP) at the Indian Institute of Technology Kharagpur (IIT-KGP). He is involved in research in the field of steganography and digital watermarking. He has published more than sixty papers in international/national journals and conference/workshop proceedings. He has more than 30 years of teaching and research experience.

Preface 6
The Organization of CSI-2015 9
Contents 11
About the Editor 14
1 A Mathematical AI-Based Diet Analysis and Transformation Model 15
Abstract 15
1 Introduction 15
2 Problem Statement 16
3 Energy Requirements and Its Evaluation 17
3.1 Nutrients Consideration 17
4 Fuzzy Arithmetic and Computation 17
4.1 Preliminaries 17
5 Tabu Search Background 18
6 Proposed Work 18
6.1 Diet Analysis Module 19
6.2 Optimization Module 19
6.3 Diet Transformation Module 19
7 Concluding Discussion 20
Declaration 21
References 21
2 Energy Efficient Measures for Sustainable Development of Data Centers 22
Abstract 22
1 Introduction 23
2 Scope of Energy Efficient Technologies and Techniques in Data Centers 24
3 Energy Saving in Electrical System 24
4 Cooling System 25
5 IT Equipment 27
6 Operation and Maintenance in Data Center 29
7 Conclusion 30
8 Future Scope 31
References 31
3 Analysis on Multiple Combinations of Series–Parallel Connections of Super Capacitors for Maximum Energy Transferring to Load in Minimum Time 33
Abstract 33
1 Introduction 33
1.1 Proposed Scheme 34
1.2 Basic Scheme 34
2 Case-1 36
3 Case-2 39
4 Case-3 41
5 Conclusion 45
References 46
4 Design and Simulation of OTA Using 45 nm Technology 47
Abstract 47
1 Introduction 47
2 Device Structure and Features 48
3 Operational Transconductance Amplifier 49
3.1 Results 51
4 Conclusion 52
References 52
5 Design and Analysis of Microstrip Patch Antenna Using DRAF 54
Abstract 54
1 Introduction 55
2 Antenna Design 55
2.1 Design of Microstrip Triangular Patch Antenna with Side Length a = 25 mm 55
2.2 Design of Microstrip Triangular Patch Antenna with Side Length a = 30 mm 57
3 Simulated Results 58
4 Conclusion 61
Acknowledgements 61
References 62
6 Principal Component Analysis-Based Block Diagonalization Precoding Algorithm for MU-MIMO System 63
Abstract 63
1 Introduction 63
1.1 Organization 65
1.2 Notation 65
2 MU-MIMO System Model 65
3 Proposed PCA-Based Precoding Algorithm 66
4 Performance Analysis 69
5 Conclusion 70
References 71
7 Low-Power High-Performance Multitransform Architecture Using Run-Time Reconfigurable Adder for FPGA and ASIC Implementation 72
Abstract 72
1 Introduction 73
2 Multitransform Architecture 73
3 Proposed Adder 74
4 Performance Evaluation and Comparison 77
4.1 FPGA Implementation 77
4.2 ASIC Implementation 78
5 Conclusion and Future Scope 80
Acknowledgements 80
References 80
8 A Review of Dynamic Scheduling Algorithms for Homogeneous and Heterogeneous Systems 82
Abstract 82
1 Introduction 82
2 Homogeneous and Heterogeneous Systems 84
2.1 Heterogeneous System 84
2.2 Homogeneous System 84
3 Review of Dynamic Scheduling Algorithms (DSA) 85
3.1 The Earliest Time First (ETF) Algorithm 85
3.2 Dynamic Level Scheduling (DLS) Algorithm 85
3.3 The Earliest Deadline First (EDF) Algorithm 86
3.4 Online Scheduling of Dynamic Task Graph (OSDTG) 86
3.5 Dynamic Load Balancing Using Task-Transfer Probabilities (DLBTTP) 86
3.6 Dynamic Task Scheduling (DTS) Algorithm 86
3.7 DLS Algorithm with Genetic Operators (DLSAGO) 87
3.8 Dynamic Task Graph Scheduling with Fault-Tolerant (FTDTGS) 87
3.9 DTS with Load Balancing (DTSLB) 87
3.10 Dynamic Load Balancing Using Genetic Algorithms (DLBGA) 87
3.11 Parallel Genetic Algorithms for Heterogeneous (PGAH) 88
3.12 Global Scheduling for Mixed-Critically (GSMC) 88
3.13 The Response Time Analysis of Global Fixed-Priority (RTAGFP) 88
3.14 New Response Time Bounds for Fixed Priority (RTBFP) 88
3.15 Load-Based Schedulability Analysis of Certificate Mixed-Criticality System (LBSCMCS) 90
4 Comparison of Dynamic Scheduling Algorithms on HMS and HTS 90
5 Conclusion and Future Work 91
References 91
9 Effective Information Retrieval Algorithm for Linear Multiprocessor Architecture 93
Abstract 93
1 Introduction 93
2 The LCQ Server 95
3 System Model 96
3.1 The Proposed Algorithm 97
4 Result and Discussion 100
5 Conclusion 100
References 101
10 Design of Energy-Efficient Random Access Memory Circuit Using Low-Voltage CMOS and High-Speed Transreceiver Logic-I I/O Standard on 28 nm FPGA 103
Abstract 103
1 Introduction 103
2 Block Diagram of Memory 104
2.1 Register Transfer Level Schematic of 64-Bit RAM 104
2.2 Top-Level View of Random Access Memory Package Pins 105
3 Analysis of Power 105
3.1 Power Consumption on 2.0 GHz Frequency 106
3.1.1 Using LVCMOS 106
3.1.2 HSTL-I 106
3.2 Power Consumption on 2.1 GHz Frequency 107
3.2.1 LVCMOS 107
3.2.2 HSTL-I 107
3.3 Power Consumption on 2.5 GHz Frequency 108
3.3.1 LVCMOS 108
3.3.2 HSTL-I 108
3.4 Power Consumption on 2.9 GHz Frequency 109
3.4.1 Using LVCMOS 109
3.4.2 Using HSTL-I 110
3.5 Power Consumption on 3.1 GHz Frequency 110
3.5.1 Using LVCMOS 110
3.5.2 HSTL-I 111
3.6 Power Consumption on 3.5 GHz Frequency 111
3.6.1 Using LVCMOS 111
3.6.2 HSTL-I 112
4 Conclusion 113
5 Future Scopes 113
References 113
11 Stub Series Terminal Logic-Based Low-Power Thermal-Aware Vedic Multiplier Design on 40-nm FPGA 115
Abstract 115
1 Introduction 116
1.1 Antyayor_Dasakepi_Sutra 116
2 Power and Thermal Analysis of Vedic Multiplier 116
2.1 Analysis of MAT, Junction Temperature, and Leakage Power 116
3 IO Standards 118
3.1 Power Analysis 118
3.2 Thermal Analysis 119
4 Conclusion 120
5 Future Scope 120
References 121
12 LVCMOS-Based Low-Power Thermal-Aware Energy-Proficient Vedic Multiplier Design on Different FPGAs 122
Abstract 122
1 Introduction 123
1.1 Example 1: Square of 8? 123
1.2 Example 2: Square of 992? 123
2 Power Scrutiny via Scaling Thermally 124
2.1 Power Scrutiny Using LVCMOS_12 I/O Standard 124
2.2 Power Scrutiny Using LVCMOS15 IO Standard 125
2.3 Power Scrutiny via LVCMOS12 I/O Standard 125
2.4 Power Scrutiny via LVCMOS I/O Set on 20 °C 126
2.5 Power Scrutiny via LVCMOS I/O Set on 30 °C 127
2.6 Power Scrutiny via LVCMOS I/O Set on 45 °C 127
3 Conclusion 128
4 Future Scope 128
References 128
13 Timing Constraints-Based High-Performance DES Design and Implementation on 28-nm FPGA 130
Abstract 130
1 Introduction 131
2 Related Work 131
3 Pin-out Report 132
4 Timing Analysis 134
4.1 Worst-Case Slack in Timing Analysis of DES Algorithm 135
4.2 Best Achievable Time in Timing Analysis of DES Algorithm 135
4.3 Timing Errors in Timing Analysis of DES Algorithm 136
4.4 Timing Scores in Timing Analysis of DES Algorithm 136
5 Static Timing Analysis 137
5.1 Setup Paths in Static Timing Analysis 137
5.2 Hold Paths in Static Timing Analysis 138
5.3 Component Switching Limits 139
6 Timing Report 139
7 Mapping Report 140
7.1 Worst-Case Slack in Mapping Report of DES Algorithm 140
7.2 Best-Case Achievement in Mapping Report of DES Algorithm 141
7.3 Timing Errors in Mapping Report of DES Algorithm 141
7.4 Timing Score in Mapping Report of DES Algorithm 141
8 Generating Clock Report 142
9 Conclusion 143
10 Future Scope 143
References 144
14 Input–Output Standard-Based Energy Efficient UART Design on 90 nm FPGA 145
Abstract 145
1 Introduction 146
2 Related Work 146
3 Objective 147
4 Results 149
4.1 High-Speed Low-Voltage Digitally Controlled Impedance 149
4.2 Low-Voltage Transistor Logic 149
4.3 Low-Voltage Complementary Metal Oxide Semiconductor 150
4.4 Peripheral Component Interconnect Extended 150
4.5 Gunning Transceiver Logic 151
4.6 High-Speed Transistor Logic I 151
4.7 High-Speed Transceiver Logic IV 152
4.8 Stub Series Terminated Logic_II_Digitally Controlled Impedance 152
4.9 Low-Voltage Digitally Controlled Impedance_15 153
4.10 Peripheral Component Interconnect 153
5 Conclusion 155
6 Future Scopes 155
References 156
15 Different Configuration of Low-Power Memory Design Using Capacitance Scaling on 28-nm Field-Programmable Gate Array 157
Abstract 157
1 Introduction 158
2 Related Work 158
3 Junction and Ambient Temperatures 159
4 Stub Series Terminated Logic 160
4.1 Junction Temperature with SSTL135 I/O Standard for Auto RAM Style 160
4.2 Junction Temperature with SSTL135I/O Standard for Distributed RAM Style 160
4.3 Junction Temperature with SSTL135 I/O Standard for Bufgdll BRAM 160
5 Thermal Analysis of Different RAM Styles 160
5.1 For frequency Range 1–10 GHz 160
5.2 Power Consumption for Capacitance 5 pF and Airflow = 250 Linear Feet per Minute 164
5.3 Power Consumption for Capacitance 50 pF and Airflow = 500 Linear Feet per Minute 165
5.4 Power Consumption for 1–10 GHz 166
6 Conclusion 166
7 Future Scope 167
References 167
16 Ardudroid Surveillance Bot 168
Abstract 168
1 Introduction 168
2 Hardware Design 169
2.1 Android Device 170
2.2 Bot Chassis 170
2.3 Microcontroller Board (Arduino UNO) 170
2.4 Bluetooth Module 171
2.5 Motor Driver Board 172
2.6 DC Motor 172
3 Electronics of the System 173
4 Software Implementation 174
5 Conclusion and Significance 177
References 177
17 Development of Cross-Toolchain and Linux Device Driver 179
Abstract 179
1 Introduction 180
2 Cross-Toolchain 180
2.1 Building a Cross-Compiler Toolchain 181
3 Porting Linux on Mini2440 182
4 Working on Qt Applications 184
5 Implementation of Character Driver 186
6 Sockets 187
7 Results and Conclusion 187
References 188
18 Design and Implementation of a Green Traffic Light Controller on FPGA Using VHDL 190
Abstract 190
1 Introduction 190
2 Traffic Light Design 191
3 Clock Gating 192
4 XPower Analyser Results 193
5 Simulation Results 194
6 Conclusion 195
References 195
19 Suboptimal Controller Design for Power System Model 196
Abstract 196
1 Introduction 196
2 Aggregation Technique 197
3 Results and Discussion 198
4 Conclusion 203
References 203
20 Designing and Simulation of S-Shaped Dielectric Resonator Antenna with Air Gap 204
Abstract 204
1 Introduction 204
2 Overview and Antenna Configuration 205
3 Simulated Results and Parametric Discussion 206
4 Conclusions 210
5 Future Scope 210
References 211
21 Trajectory Generation for Driver Assistance System 212
Abstract 212
1 Introduction 213
2 Block Components and Process Implemented 214
2.1 Sensors 214
2.2 Radar 215
2.3 Intervehicle Communication 215
3 Algorithms 218
4 Result 218
5 Conclusion 220
6 Future Scope 220
References 220
22 Performance Enhancement of MRPSOC for Multimedia Applications 221
Abstract 221
1 Introduction 222
2 Proposed System 222
2.1 Reconfigurable Instruction Set Processor 223
2.2 Architecture of RFU 224
2.3 Methodology for MRPSOC 225
2.3.1 Profiling Step 226
2.3.2 Identifying Step 226
2.3.3 Optimization Step 226
2.3.4 Assignment Step 226
2.4 Algorithm for MRPSOC 226
2.5 Data-Level Parallelism 227
2.6 Instruction-Level Parallelism 227
2.7 Memory-Level Parallelism 228
3 Simulation Results 228
3.1 Simulation of MPSOC 228
3.2 Simulation of Integrated Processor (MRPSOC and Multigrain Parallelism) 230
4 Conclusion 230
References 231
23 A New CPU Scheduling Algorithm Using Round-robin and Mean of the Processes 232
Abstract 232
1 Introduction 233
2 Literature Overview 234
2.1 Terminology 234
2.2 Related Works 235
3 Proposed Model 235
3.1 Assumptions 235
3.2 Algorithm 235
3.3 Proposed Work Flow 236
4 Illustrative Examples and Discussion 237
5 Conclusion and Future Scope 240
References 241
24 Synchronization of Two Chaotic Oscillators Through Threshold Coupling 242
Abstract 242
1 Introduction 242
2 Literature Overview 243
3 Modeling and Simulation of Chaotic System 244
3.1 Dynamic Modeling of Single System 244
3.2 Coupled Systems Through Threshold Controller 244
4 Simulation Result of Coupled System Through Threshold Controller Coupling 246
5 Conclusion 247
Acknowledgements 247
References 247
25 L3C Model of High-Performance Computing Cluster for Scientific Applications 249
Abstract 249
1 Introduction 250
2 Performance of HPCC 250
3 Scientific Applications on HPCC 251
4 Factors Governing Performance for Scientific Applications 251
5 Models for Understanding HPCC Performance for Scientific Applications 252
6 L3C Model of HPCC for Scientific Applications 256
7 Implications of L3C Model 258
8 Conclusions 259
References 260
26 Design and Development of Digital Energy Meter on FPGA 261
Abstract 261
1 Introduction 262
2 FPGA Architecture and Design Flow 263
2.1 FPGA and Its Architecture 263
2.2 FPGA Design Flow 264
3 Advantages of FPGA 264
4 Implementation Details 265
4.1 ADC Module 265
4.2 Zero Crossing Detector 266
4.3 Counter Module 266
4.4 Peak Detector 266
4.5 Float to ASCII Conversion 266
4.6 Communication Module 266
5 IP Cores 267
5.1 Floating-Point Core 267
5.2 CORDIC 268
6 Test Results 268
7 Conclusion 272
Acknowledgements 273
References 273
27 Design of a Hypothetical Processor Using Re-configurable Logic in VHDL 274
Abstract 274
1 Introduction 274
2 Design of Processor 276
2.1 Arithmetic, Logical, and Shift Unit 276
2.2 Shifter Unit 278
2.3 Register File 279
3 Simulation 280
4 Conclusion 282
References 282
28 Aspects Involved in the Modeling of PV System, Comparison of MPPT Schemes, and Study of Different Ambient Conditions Using P& O Method
Abstract 283
1 Introduction 283
2 Mathematical Model of Photovoltaic Cell 284
2.1 Photovoltaic Cell 284
2.2 Modeling the Photovoltaic Array 285
3 Maximum Power Point Tracking and Converters Used in PV System 289
3.1 Need of MPPT and Converters 289
3.2 MPPT Schemes and Their Comparison 289
3.3 DC–DC Boost Converter—Designing 292
4 Perturbation and Observation Technique 294
5 Model of Used Flowchart in Simulink 294
6 Simulation Result 296
7 Conclusion 300
References 300
29 A Novel Approach for Data Classification Using Neutrosophic Entropy 302
Abstract 302
1 Introduction 302
2 Dataset Details 304
3 Classification Based on Fuzzy Probability 305
3.1 Basic Criteria for Determining Fuzzy Probability 305
3.2 Basic Criteria for Determining Fuzzy Entropy 306
4 Classification Based on Neutrosophic Probability 306
4.1 Basic Criteria for Determining Neutrosophic Probability 307
4.2 Basic Criteria for Neutrosophic Entropy 308
5 Implementation of Fuzzy Probability and Neutrosophic Probability on Appendicitis Dataset 308
6 Experiments and Results 310
7 Conclusion and Future Scope 313
References 314
30 SDN Layer 2 Switch Simulation Using Mininet and OpenDayLight 315
Abstract 315
1 Introduction 315
1.1 Problem Definition 316
2 Theory 316
2.1 OpenFlow 316
2.2 OpenDaylight 318
2.3 Layer 2 Switch 319
3 Simulation Design 320
3.1 Network Design 320
3.2 SDN Controller 320
3.3 Procedure for Simulation 321
4 Result 321
5 Conclusion 322
References 323
31 An Architectural Design for Knowledge Asset Management System 324
Abstract 324
1 Introduction 325
2 Knowledge Asset Management Processes and Actors 327
3 Architecture of Knowledge Asset Management (KAM) System 329
4 Comparative Analysis and Advantages of the Proposed System 331
5 Conclusion 332
References 333