3D Integration in VLSI Circuits

Katsuyuki Sakuma is a research staff member at the IBM T. J. Watson Research Center. Currently, he is also a Visiting Professor at the Department of Biomedical Engineering, Tohoku University, Japan. He has over 19 years of experience of researching 3D integration technologies and performing various semiconductor packaging research and development projects. His research interests include 3D integration technologies, bonding technologies, and advanced packaging. He has published more than 85 peer-reviewed journal papers and conference proceeding papers, including three book chapters in the semiconductor and electronic packaging area. He also holds over 35 issued or pending U.S. and international patents. He has been recognized with the IBM Eleventh Invention Achievement Award in 2017 and an Outstanding Technical Achievement Award (OTAA) in 2015 for his contribution and leadership in the area of 3D integration technology development. He was also given the 2018 Exceptional Technical Achievement Award from IEEE Electronics Packaging Society and the 2017 Alumni Achievement Award from his Alma Mater, the School of Engineering at Tohoku University, for his contribution to 3D chip stack technology development in the electronics packaging industry. He was co-recipient of the IEEE CPMT Japan Society Best Presentation Award in 2012, and the IMAPS "Best of Track" Outstanding Paper Award in 2015. Dr. Sakuma received his B.S. and M.S. degrees from Tohoku University, and the Ph.D. degree from Waseda University, Japan. He is currently serving as an Associate Editor for IEEE Transactions on Components, Packaging and Manufacturing Technology (CPMT). He served as an Associate Editor of the Institute of Electronics, Information and Communication Engineers (IEICE, Japan) from 2003 until 2005. He has served as committee member of the IEEE ECTC Interconnections sub-committee since 2012, for the IEEE International Conference on 3D System Integration (IEEE 3DIC) since 2016, and for the IEEE International Reliability Physics Symposium (IEEE IRPS) since 2017. He has been a senior member of IEEE since 2012.

Three-Dimensional Integration: Technology and Design. Three-Dimensional System-in-Package for Application-Specific Integrated Circuit and Three-Dimensional Dynamic Random-Access Memory Integration. A New Class of High-Capacity, Resource-Rich Field-Programmable Gate Arrays Enabled by Three- Dimensional Integration Chip-Stacked Silicon Interconnect Technology. Challenges in 3D Integration. Wafer-Level Three-Dimensional Integration Using Bumpless Interconnects and Ultrathinning. Three-Dimensional Integration Stacking Technologies for High-Volume Manufacturing by Use of Wafer-Level Oxide-Bonding Integration. Toward Three-Dimensional High Density. Novel Platforms and Applications Using Three-Dimensional and Heterogeneous Integration Technologies.