Circuit Design for Reliability (eBook)

Contents 6
1 Introduction 8
2 Recent Trends in Bias Temperature Instability 12
1 Introduction 12
2 Brief Overview of BTI 13
3 Static BTI 13
4 Dynamic BTI 14
5 Similarity Between BTI Relaxation and Low-Frequency Noise 15
6 Semi-quantitative Model for BTI Relaxation 15
7 Properties of Individual Defects 17
8 Modeling Properties of Individual Defects 19
9 BTI Distribution in Deeply-Scaled FETs 21
10 Technological Solutions 22
11 Improving PBTI with Rare-Earth Incorporation 23
12 Improving NBTI in High-Mobility SiGe pFETs 23
References 25
3 Charge Trapping Phenomena in MOSFETS: From Noise to Bias Temperature Instability 27
1 Introduction 27
2 Charge Trapping Events as a Source of Noise 30
3 Power Spectrum of the RTN Noise due to a Single Trap 31
4 Approximation for Excitation Frequencies Higher than the Noise Frequency 34
5 Average Power Spectrum of the RTN Noise due to the Ensemble of Traps 36
6 Square Wave Excitation 36
7 Variability in the Power Spectrum of the RTN Noise due to the Ensemble of Traps 39
8 Experimental Results 41
9 The Charge Trapping Component of Bias Temperature Instability 42
References 50
4 Atomistic Simulations on Reliability 53
1 Introduction 53
2 Discrete Impurity Effects 54
2.1 Some General Considerations 54
2.2 Drift-Diffusion Simulations of Discrete Impurity Effects 54
2.3 Monte Carlo Device Simulations of Discrete Impurity Effects 57
3 Random Telegraph Signal 61
3.1 Importance of Random Trap Fluctuations 61
3.2 Monte Carlo Device Simulations of Random Traps at the Semiconductor/Oxide Interface 64
4 Conclusions 68
4.1 Local Surface Potential Fluctuations 69
4.2 Fluctuation in Carrier Mobility 71
4.3 Interface Conditions 71
References 72
5 On-Chip Characterization of Statistical Device Degradation 74
1 Introduction 74
1.1 Transient Change in Device Parameters 75
1.2 Measurement Requirements 76
2 Circuit Structures for the Measurement of Device Degradation 77
2.1 Measurements Using Off-Chip Equipment 77
2.2 On-Chip Measurements 78
3 BTIarray for Statistical Characterization of Device Degradation 79
3.1 Stress and Recovery Time Overlapping 79
3.2 Circuit Structure of BTIarray 81
3.3 Implementation Example 84
3.4 Measurement Automation Through Scripting 85
3.5 Measurement Accuracy 87
4 Characterization Example of Statistical Degradations 88
4.1 Measurement Scenario 88
4.2 Threshold Voltage Shifts for Small DUTs 90
4.3 Statistical Model Parameter Extraction for NBTI 93
4.4 Measurement Efficiency 95
5 Chapter Summary 95
References 96
6 Compact Modeling of BTI for Circuit Reliability Analysis 98
1 Introduction 98
1.1 BTI Aging Models: Challenges and Needs 100
2 Reliability Physics: Device-Level Modeling of BTI 101
2.1 Static BTI Models 102
2.1.1 Reaction: Diffusion Based Static BTI Model 102
2.1.2 Trapping/De-trapping Based Static BTI Model 104
2.2 BTI Models Under Random Stress Patterns 106
2.2.1 Reaction: Diffusion Based Aging Model for Random Input 107
2.2.2 Trapping/De-Trapping Based Random Input Aging Model 110
2.3 Long-Term BTI Model Under DVS 114
2.3.1 Long-Term BTI Model Based on Reaction–Diffusion 114
2.3.2 Long-Term BTI Model Based on Trapping/De-Trapping 115
3 Circuit Aging Simulation 117
3.1 Aging Analysis: Digital Circuits 118
3.2 Aging Analysis: AMS Circuits 119
4 Summary 120
References 122
7 Circuit Resilience Roadmap 125
1 Introduction 125
2 Trends in Technology 127
2.1 Manufacturing Variations 127
2.2 Aging 129
2.3 Particle Strikes 130
3 Trends in Memory 132
3.1 CMOS SRAM 132
3.2 Resilience Key Parameters 134
3.3 Design Trends and Considerations 135
3.4 SRAM Scaling Trends 137
4 Trends in Logic 139
4.1 Influence of Process Variations 139
4.2 Scaling Trends 142
5 Conclusion 145
References 146
8 Layout Aware Electromigration Analysis of Power/Ground Networks 148
1 Introduction to Electromigration 148
1.1 Basic Concepts 148
1.2 Classical Theories 149
1.2.1 Black's Equation 149
1.2.2 Blech Length Effect 150
1.3 Affecting Factors 151
1.3.1 Current Density 151
1.3.2 Temperature 152
1.3.3 Wire Length 152
1.3.4 Interconnect Structure 153
1.3.5 Activation Energy 154
1.3.6 Diffusion Paths 154
2 Physical Simulation of EM 155
2.1 Background 155
2.2 Balance of Atom Concentration 156
2.3 Simulation Setup and Result 157
3 Variation-Aware Compact MTTF Model 157
3.1 Variation Sources 157
3.1.1 CMP Dishing 157
3.1.2 EPE 158
3.2 Compact Model 159
3.2.1 Observations 159
3.2.2 Critical Region 160
Definition 1 160
3.2.3 Compact Model 161
4 Full-Chip EM Analysis 163
4.1 Power Grid Model 163
4.2 Effective jL Product Extraction 164
4.3 Analytical Lifetime Calculation 165
4.4 Global Current Redistribution 167
4.5 VEMA Flow 168
5 Experimental Results 169
Definition 2 173
References 175
9 Power-Gating for Leakage Control and Beyond 177
1 Introduction 178
2 Design Issues for Nanometric CMOS Circuits 179
2.1 Sub-threshold Leakage Power Consumption 179
2.2 Sources of Variability 180
3 Power-Gating for Leakage Power Reduction 182
3.1 Power-Gating Basics 182
3.2 Clustered Row-Based Sleep Transistor Insertion Methodology 184
3.2.1 Peak Current Estimation 185
3.2.2 Sleep Transistor Sizing 186
3.2.3 Power-Gating Strategies 188
3.2.4 Layout Modification 188
4 Clustered Tunable Power-Gating for PV Compensation 190
4.1 Modeling Process Variations and Timing Yield 190
4.2 Controlling Performance with Tunable Sleep-Transistors 191
4.3 Design Issues and Architectures 193
4.3.1 Design Issues 193
4.3.2 Architectures 193
4.3.3 Design Flow and Results 194
5 Clustered Power-Gating for NBTI-Induced Aging Minimization 196
5.1 Background and Models 197
5.2 Power-Gating and Aging Reduction 199
5.3 Design Issues and Architectures 200
5.3.1 Design Issues 200
5.3.2 Architectures 202
5.3.3 Design Flow and Results 203
References 205
10 Soft Error Rate and Fault Tolerance Techniques for FPGAs 208
1 Introduction 208
2 FPGAs Under Soft Errors 209
2.1 Single Event Effects on SRAM-Based FPGAs 210
2.2 Single Event Effects on Flash-Based FPGAs 210
2.3 Single Event Effects on Antifuse-Based FPGAs 212
3 Fault Tolerance Techniques for FPGAs 213
3.1 SRAM-Based FPGAs 214
3.2 FLASH-Based and Antifuse-Based FPGAs 218
4 Radiation Test Methodologies to Predict and Measure SER in FPGAs 218
References 221
11 Low Power Robust FinFET-Based SRAM Design in Scaled Technologies 223
1 Introduction 223
1.1 Alternate Device Structures 224
1.2 Fundamentals of FinFETs 225
1.3 Fundamentals of 6 T SRAMs 226
2 Co-optimization of Fin Ratio and Fin Thickness 227
3 Joint Optimization of Fin Height, Fin Thickness, Oxide Thickness, Supply Voltage and Threshold Voltage 230
4 Fin Rotation and Orientation 233
5 Spacer Thickness Optimization 235
5.1 Symmetric Spacer Optimization 235
5.2 Asymmetric Drain Spacer Extension FinFETs 237
6 SRAMs based on Asymmetrically Doped (AD) FinFETs 240
7 Independent Gate FinFETs 242
7.1 Bi-mode Independent Gate FinFET SRAMs 243
7.2 Tri-Mode Independent Gate FinFET SRAMs 246
7.3 Pass Gate Feedback in FinFET SRAMs 249
8 Summary 251
References 252
12 Variability-Aware Clock Design 254
1 Introduction 254
1.1 Definitions 256
1.2 Robustness 256
2 Variability 257
2.1 Types of Variation 257
2.1.1 Process 258
2.1.2 Voltage 258
2.1.3 Temperature 258
2.1.4 Crosstalk 259
2.2 Impact of Variation Models 259
2.3 Common Industry Models 261
2.4 Requirements for Variation Models 261
2.5 Analysis Methodologies 262
3 Clock Trees 263
4 Clock Meshes 266
References 269