VLSI Implementations for Image Communications (eBook)

Front Cover 1
VLSI Implementations for Image Communications 4
Copyright Page 5
Table of Contents 10
INTRODUCTION TO THE SERIES: "Advances In Image Communication" 6
Preface 8
Chapter 1. Video Coding Techniques: An Overview 12
1. INTRODUCTION 12
2. QUANTIZATION 13
3. PREDICTIVE IMAGE CODING 20
4. ENTROPY CODING 25
5. ORTHOGONAL TRANSFORMS 30
6. MOTION ESTIMATION/COMPENSATION 35
7. SUBBAND PROCESSING 40
8. VIDEO CODING EXAMPLES 47
9. SUMMARY 54
References: 54
Chapter 2. VLSI Implementation Strategies 60
1. INTRODUCTION 60
2. IMPLEMENTATION COST 62
3. HARDWARE RELATED CHARACTERISTICS OF ALGORITHMS 63
4. MULTIPROCESSOR ARCHITECTURES 66
5. INTERACTION BETWEEN ALGORITHMS AND ARCHITECTURES 75
6. CONCLUSION 78
7. REFERENCES 78
Chapter 3. Mapping Algorithms onto VLSI Architectures 80
1. Introduction 80
2. The Design Problem 82
3. Scheduling and Allocation 91
4. A Methodology for Mapping Algorithms Onto Architectures 107
5. Concluding Remarks 122
References 123
Chapter 4. Multiprocessor DSPs for Low Bit Rate Video Codec 128
1. Introduction 128
2. Video coding requirements 129
3. Multiprocessor DSP System for Video Codec 133
4. DSP Architecture and Design 138
5. A single board video codec using multiple IDSP 145
6. Future trends in DSP 156
7. References 159
Chapter 5. A Real-Time Parallel Processor for Video Signal Processing 160
1. INTRODUCTION 160
2. VSP ARCHITECTURE 161
3. VSPM STRUCTURE 167
4. VIDEO PROCESSING SYSTEMS 171
5. CONCLUSION 179
6. REFERERENCES 180
Chapter 6. High Throughput Digital Filters 182
1. Introduction 182
2. Transversal Filters 183
3. Special Transversal Filters 204
4. Parallelization and Time-Sharing - Matching the Troughput Requirements 208
5. Recursive Filters 213
6. Programmable Two-Dimensional Transversal Filters 217
7. Concluding Remarks 222
References 222
Chapter 7. Orthogonal Transforms 228
1. INTRODUCTION 228
2. THE DISCRETE COSINE TRANSFORM : ALGORITHMIC VIEWPOINT 230
3. THE DISCRETE COSINE TRANSFORM : ARCHITECTURAL VIEWPOINT 237
4. ARCHITECTURE OF A DCT PROCESSOR: AN EXAMPLE 256
5. CONCLUSION 258
6. ACKNOWLEDGEMENTS 259
7. REFERENCES 259
Chapter 8. Algorithms and VLSI Architectures for Motion Estimation 262
1. INTRODUCTION 262
2. MOTION ESTIMATION ALGORITHMS 263
3. VLSI ARCHITECTURES AND IMPLEMENTATIONS FOR BMA 268
4. VLSI ARCHITECTURES AND IMPLEMENTATIONS FOR PRA 287
5. CONCLUSION 289
ACKNOWLEDGEMENT 290
REFERENCES 290
Chapter 9. VLSI Architectures and Implementations for Vector Quantization 294
1 Vector Quantization Algorithms 294
2 Full Search Techniques 297
3 Tree Search Schemes 306
4 IC Design Strategy for VQ 315
5 Summary 319
References 319
Chapter 10. DPCM-Codecs 322
1. INTRODUCTION 322
2. DPCM ALGORITHMS 323
3. VLSI ARCHITECTURES FOR 2D DPCM 326
4. CIRCUIT TECHNIQUES FOR SPEEDUP OF DPCM IMPLEMENTATION 338
5. REALIZATION TECHNIQUES FOR LINE DELAYS AND FORMATTERS 343
6. FURTHER ASPECTS 348
7. DESIGN EXAMPLES 350
8. CONCLUSION 353
REFERENCES 353
Chapter 11. Design of High-Throughput Entropy Codec 356
1. INTRODUCTION 356
2. ALGORITHM OVERVIEW AND SYSTEM CONSIDERATIONS 358
3. ARCHITECTURES FOR THE VLD 361
4. AN ENTROPY CODEC FOR HDTV APPLICATIONS 366
5. OTHER TECHNIQUES FOR HIGH-SPEED IMPLEMENTATIONS 371
6. CONCLUSION 372
ACKNOWLEDGEMENT 373
REFERENCES 373
Chapter 12. Parallel Processing and Pipelining in Huffmann Decoder 376
1. Introduction 376
2. Huffman Decoder using Finite State Machines 378
3. Multiple Source Interleaved Decoder 382
4. Table Look-Up Decoder 383
5. Pipelined Decoder Using Look-Ahead 384
6. Incremental Block Decoder 386
7. Parallel and Pipelined Decoder using Look-Ahead 388
8. Block Postcomputation Decoder 389
9. Bit-Positioning Postcomputation 394
10. Source Control Decoder 394
11. Concurrent Loss-Less Coder 394
12. Loss-Less Coder with Maximum Code Word Length 399
13. Efficient Lossless Coder with Conditional Coding 400
14. Conclusion 402
15. Acknowledgement 403
16. References 404
Subject Index 408