Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications - Gaurav Singh, Sandeep Kumar Shukla

Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications

Buch | Softcover
154 Seiten
2014
Springer-Verlag New York Inc.
978-1-4899-8702-0 (ISBN)
106,99 inkl. MwSt
Human lives are getting increasingly entangled with technology, especially comp- ing and electronics. At each step we take, especially in a developing world, we are dependent on various gadgets such as cell phones, handheld PDAs, netbooks, me- cal prosthetic devices, and medical measurement devices (e.g., blood pressure m- itors, glucometers). Two important design constraints for such consumer electronics are their form factor and battery life. This translates to the requirements of reduction in the die area and reduced power consumption for the semiconductor chips that go inside these gadgets. Performance is also important, as increasingly sophisticated applications run on these devices, and many of them require fast response time. The form factor of such electronics goods depends not only on the overall area of the chips inside them but also on the packaging, which depends on thermal ch- acteristics. Thermal characteristics in turn depend on peak power signature of the chips. As a result, while the overall energy usage reduction increases battery life, peak power reduction in?uences the form factor. One more important aspect of these electronic equipments is that every 6 months or so, a newer feature needs to be added to keep ahead of the market competition, and hence new designs have to be completed with these new features, better form factor, battery life, and performance every few months. This extreme pressure on the time to market is another force that drives the innovations in design automation of semiconductor chips.

Related Work.- Background.- Low-Power Problem Formalization.- Heuristics for Power Savings.- Complexity Analysis of Scheduling in CAOS-Based Synthesis.- Dynamic Power Optimizations.- Peak Power Optimizations.- Verifying Peak Power Optimizations Using SPIN Model Checker.- Epilogue.

Erscheint lt. Verlag 18.9.2014
Zusatzinfo XXX, 154 p.
Verlagsort New York
Sprache englisch
Maße 155 x 235 mm
Themenwelt Informatik Weitere Themen CAD-Programme
Technik Elektrotechnik / Energietechnik
ISBN-10 1-4899-8702-9 / 1489987029
ISBN-13 978-1-4899-8702-0 / 9781489987020
Zustand Neuware
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