Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications (eBook)
XXX, 154 Seiten
Springer New York (Verlag)
978-1-4419-6481-6 (ISBN)
Human lives are getting increasingly entangled with technology, especially comp- ing and electronics. At each step we take, especially in a developing world, we are dependent on various gadgets such as cell phones, handheld PDAs, netbooks, me- cal prosthetic devices, and medical measurement devices (e.g., blood pressure m- itors, glucometers). Two important design constraints for such consumer electronics are their form factor and battery life. This translates to the requirements of reduction in the die area and reduced power consumption for the semiconductor chips that go inside these gadgets. Performance is also important, as increasingly sophisticated applications run on these devices, and many of them require fast response time. The form factor of such electronics goods depends not only on the overall area of the chips inside them but also on the packaging, which depends on thermal ch- acteristics. Thermal characteristics in turn depend on peak power signature of the chips. As a result, while the overall energy usage reduction increases battery life, peak power reduction in?uences the form factor. One more important aspect of these electronic equipments is that every 6 months or so, a newer feature needs to be added to keep ahead of the market competition, and hence new designs have to be completed with these new features, better form factor, battery life, and performance every few months. This extreme pressure on the time to market is another force that drives the innovations in design automation of semiconductor chips.
Preface 6
Acknowledgments 17
Contents 18
List of Figures 22
List of Tables 24
Acronyms 25
1 Introduction 26
1.1 Motivation 26
1.2 High-Level Synthesis 27
1.2.1 CDFG-Based High-Level Synthesis 28
1.2.2 Esterel-Based High-Level Synthesis 30
1.2.3 CAOS-Based High-Level Synthesis 30
1.3 Low-Power Hardware Designs 31
1.3.1 Power-Aware High-Level Synthesis 32
1.4 Verification of Power-Optimized Hardware Designs 34
1.4.1 Verification Using CAOS 34
1.5 Problems Addressed 35
1.6 Organization 36
2 Related Work 38
2.1 High-Level Synthesis 38
2.1.1 C-Based Languages and Tools 38
2.1.2 Other Languages and Tools 39
2.2 Low-Power High-Level Synthesis 39
2.2.1 Dynamic Power Reduction 39
2.2.2 Peak Power Reduction 42
2.2.3 Summary -- Low-Power High-Level Synthesis Work 43
2.3 Power Estimation Using High-Level Models 43
2.4 Verification of High-Level Models 46
2.4.1 SpecC 47
2.4.2 SystemC 47
2.4.3 Other Work 48
2.4.4 Summary -- High-Level Verification Work 48
3 Background 50
3.1 CDFG-Based High-Level Synthesis 50
3.2 Concurrent Action-Oriented Specifications 51
3.2.1 Concurrent Execution of Actions 51
3.2.2 Mutual Exclusion and Conflicts 52
3.2.3 Hardware Synthesis 52
3.2.4 Example 53
3.3 Power Components 54
3.3.1 Average Power 54
3.3.2 Transient Characteristics of Power 55
3.3.3 Low-Power High-Level Synthesis 55
3.4 Complexity Analysis of Algorithms 56
3.4.1 NP-Completeness 56
3.4.2 Approximation Algorithm 56
3.5 Formal Methods for Verification 57
3.5.1 Model Checking 58
4 Low-Power Problem Formalization 60
4.1 Definitions 60
4.2 Other Details 63
4.2.1 Schedule of a Design 63
4.2.2 Re-scheduling of Actions 64
4.2.3 Cost of a Schedule 64
4.2.4 Low-Power Goal 65
4.2.5 Factorizing an Action 65
4.3 Formalization of Low-Power Problems 66
4.3.1 Peak Power Problem 66
4.3.2 Dynamic Power Problem 66
4.3.3 Peak Power Problem Is NP-Complete 67
4.3.4 Dynamic Power Problem Is NP-Complete 67
5 Heuristics for Power Savings 69
5.1 Basic Heuristics 70
5.1.1 Peak Power Reduction 70
5.1.2 Dynamic Power Reduction 72
5.1.3 Example Applications 74
5.2 Refinements of Above Heuristics 77
5.2.1 Re-scheduling of Actions 77
5.2.2 Factorizing and Re-scheduling of Actions 81
5.2.3 Functional Equivalence 83
5.2.4 Example Applications 86
6 Complexity Analysis of Scheduling in CAOS-Based Synthesis 89
6.1 Related Background 90
6.1.1 Confluent Set of Actions 90
6.1.2 Peak Power Constraint 90
6.2 Scheduling Problems Without a Peak Power Constraint 90
6.2.1 Selecting a Largest Non-conflicting Subset of Actions 90
6.2.2 Constructing Minimum Length Schedules 94
6.3 Scheduling Problems Involving a Power Constraint 96
6.3.1 Packing Actions in a Time Slot Under Peak Power Constraint 97
6.3.2 Maximizing Utility Subject to a Power Constraint 99
6.3.3 Combination of Makespan and Power Constraint 100
6.3.4 Approximation Algorithms for MM-PP 103
6.3.5 Approximation Algorithms for MPP-M 105
7 Dynamic Power Optimizations 107
7.1 Related Background 107
7.1.1 Clock-Gating of Registers 107
7.1.2 Operand Isolation 107
7.2 Clock-Gating of Registers 108
7.3 Insertion of Gating Logic 110
7.3.1 Other Versions of Algorithm 2 114
7.4 Experiment and Results 115
7.4.1 Algorithm 1 115
7.4.2 Algorithm 2 117
7.4.3 RTL Power Estimation 122
7.5 Summary 124
8 Peak Power Optimizations 126
8.1 Related Background 127
8.2 Formalization of Peak Power Problem 129
8.3 Peak Power Reduction Algorithm 130
8.3.1 Handling Combinational Path Dependencies 131
8.4 Experiments and Results 133
8.4.1 Designs 133
8.4.2 Gate-Level Average Power and Peak PowerComparisons 134
8.4.3 Effects on Latency, Area, and Energy 134
8.4.4 RTL Activity Reduction 135
8.5 Summary 136
8.6 Issues Related to Proposed Algorithm 136
9 Verifying Peak Power Optimizations Using SPIN Model Checker 137
9.1 Related Background 138
9.2 Formal Description of CAOS-Based High-Level Synthesis 140
9.2.1 Hardware Description 140
9.2.2 Scheduling of Actions 141
9.3 Correctness Requirements for CAOS Designs 144
9.3.1 AOA Semantics 144
9.3.2 Concurrent Semantics 144
9.3.3 Comparing Two Implementations 145
9.4 Converting CAOS Model to PROMELA Model 146
9.4.1 Why SPIN? 146
9.4.2 Generating PROMELA Variables and Processes 146
9.4.3 Adding Scheduling Information to PROMELA Model 146
9.4.4 Sample PROMELA Models 148
9.5 Formal Verification Using SPIN 150
9.5.1 Verifying Correctness Requirement 1 (CR-1) 150
9.5.2 Verifying Correctness Requirement 2 (CR-2) 150
9.5.3 Verifying Correctness Requirement 3 (CR-3) 151
9.5.4 Sample Experiments 152
9.6 Summary 153
10 Epilogue 162
References 165
Index 171
| Erscheint lt. Verlag | 23.7.2010 |
|---|---|
| Zusatzinfo | XXX, 154 p. |
| Verlagsort | New York |
| Sprache | englisch |
| Themenwelt | Informatik ► Weitere Themen ► CAD-Programme |
| Technik ► Elektrotechnik / Energietechnik | |
| Schlagworte | CAOS • Circuit Design • Concurrent Action-Oriented Specifications • Embedded Systems • Formal Verification • High-level synthesis • Integrated circuit • Low-Power Design • Model |
| ISBN-10 | 1-4419-6481-9 / 1441964819 |
| ISBN-13 | 978-1-4419-6481-6 / 9781441964816 |
| Haben Sie eine Frage zum Produkt? |
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