Shortcut to Accurate Reliability Prediction

The traditional high-temperature operating life (HTOL) test is based on the outdated JEDEC standard that has not been supported or updated for many years. The major drawback of this method is that it is not based on a model that predicts failures in the field. Nonetheless, the electronics industry continues to provide data from tests of fewer than 100 parts, subjected to their maximum allowed voltages and temperatures for as many as 1000 h. The result based on zero, or a maximum of 1, failure out of the number of parts tested does not actually predict. This null result is then fit into an average acceleration factor (AF), which is the product of a thermal factor and a voltage factor. The result is a reported failure rate as described by the standard failure in time (FIT, also called Failure unIT) model, which is the number of expected failures per billion part hours of operation. FIT is still an important metric for failure rate in today’s technology; however, it does not account for the fact that multiple failure mechanisms simply cannot be averaged for either thermal or voltage AFs.

One of the major limitations of advanced electronic systems qualification, including advanced microchips and components, is providing reliability specifications that match the variety of user applications. The standard HTOL qualification that is based on a single high-voltage and high-temperature burn-in does not reflect actual failure mechanisms that would lead to a failure in the field. Rather, the manufacturer is expected to meet the system’s reliability criteria without any real knowledge of the possible failure causes or the relative importance of any individual mechanism. More than this, as a consequence of the nonlinear nature of individual mechanisms, it is impossible for the dominant mechanism at HTOL test to reflect the expected dominant mechanism at operating conditions, essentially sweeping the potential cause of failure under the rug while generating an overly optimistic picture for the actual reliability.

Two problems exist with the current HTOL approach, as recognized by JEDEC in publication JEP122G: (1) multiple failure mechanisms actually compete for dominance in our modern electronic devices and (2) each mechanism has a vastly different voltage and temperature AFs depending on the device operation. This more recent JEDEC publication recommends explicitly that multiple mechanisms should be addressed in a sum-of-failure-rates approach. We agree that a single point HTOL test with zero failures can, by no means, account for a multiplicity of competing mechanisms.

In order to address this fundamental limitation, we developed a special multiple-mechanism qualification approach that allows companies to tailor specifications to a variety of customers’ needs. This approach will work with nearly any circuit to design a custom multiple HTOL (M-HTOL) test at multiple conditions and match the results with the foundrys’ reliability models to make accurate FIT calculations based on specific customers’ environments including voltage, temperature, and speed.

Fortunately, for today’s sophisticated device manufacturer, we offer a unique and verifiable solution that gives the supplier a verifiably more accurate way to actually predict the expected field failure rate, FIT, based on the user’s operating conditions. The chip foundry provides the manufacturer with very complex reliability calculators designed for each technology’s process. The manufacturer then chooses specific accelerated tests that can be matched with the foundry’s reliability models, and a simple solution for the expected failure rate (FIT) can be found for any user’s expected applications. These models should be trusted by the manufacturer since they trust the models of the foundry. This way, there is confidence from the foundry to the user, and we can make believable reliability predictions in the field (Figure 1.1).

This approach fits the highly developed and sophisticated models of the foundry based on years of knowledge and testing of the physical failure mechanisms. These mechanisms are known inherently to lead to degradation and ultimately to a chip failure. The approach described herein puts this knowledge in the hands of the chip designers allowing for qualification at any expected operating conditions. This way, the same product may accommodate additional potential markets by selling the same design for higher reliability applications with broader operating margins or higher performance applications where long life is not as critical.

The traditional single-model HTOL gives an unrealistically low value for the expected FIT, and customers invariably find that their application shows a much higher reported failure rate than what was provided by the supplier using the traditional approach. Our M-HTOL matrix methodology will give a more accurate prediction for the expected field failure rate that is based on the actual test data and on the reliability models provided by the foundry to the chip designer. This way, the designer has a much more dependable picture for device reliability, and the customer will be satisfied that his design will match their customer’s expectations for performance life.