Efficient Test Methodologies for High-Speed Serial Links
Seiten
2012
Springer (Verlag)
978-94-007-3094-6 (ISBN)
Springer (Verlag)
978-94-007-3094-6 (ISBN)
Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques.
An Efficient Jitter Measurement Technique.- BER Estimation for Linear Clock and Data Recovery Circuit.- BER Estimation for Non-linear Clock and Data Recovery Circuit.- Gaps in Timing Margining Test.- An Accurate Jitter Estimation Technique.- A Two-Tone Test Method for Continuous-Time Adaptive Equalizers.- Conclusions.
| Reihe/Serie | Lecture Notes in Electrical Engineering ; 51 |
|---|---|
| Zusatzinfo | XII, 98 p. |
| Verlagsort | Dordrecht |
| Sprache | englisch |
| Maße | 155 x 235 mm |
| Themenwelt | Mathematik / Informatik ► Informatik ► Netzwerke |
| Mathematik / Informatik ► Informatik ► Theorie / Studium | |
| Informatik ► Weitere Themen ► Hardware | |
| Technik ► Elektrotechnik / Energietechnik | |
| Schlagworte | BER Estimation • Clock and Data Recovery (CDR) • Design-for-Test (DFT) • High Speed IO Test • Integrated Circuits • Jitter Measurement |
| ISBN-10 | 94-007-3094-2 / 9400730942 |
| ISBN-13 | 978-94-007-3094-6 / 9789400730946 |
| Zustand | Neuware |
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