System Designer's Guide to VHDL-AMS (eBook)

Front Cover 1
The System Designer's Guide to VHDL-AMS:Analog, Mixed-Signal, and Mixed-Technology Modeling 6
Copyright Page 7
Contents 10
Preface 20
Chapter 1. Fundamental Concepts 28
1.1 Modeling Systems 29
1.2 Domains and Levels of Modeling 32
1.3 Modeling Languages 40
1.4 VHDL-AMS Modeling Concepts 42
1.5 Learning a New Language: Lexical Elements and Syntax 53
Exercises 62
Chapter 2. Scalar Data Types, Natures and Operations 66
2.1 Constants and Variables 67
2.2 Scalar Types 70
2.3 Type Classification 84
2.4 Scalar Natures 88
2.5 Attributes of Scalar Types and Natures 93
2.6 Expressions and Operators 97
Exercises 99
Chapter 3. Sequential Statements 102
3.1 If Statements 103
3.2 Case Statements 106
3.3 Null Statements 111
3.4 Loop Statements 113
3.5 Assertion and Report Statements 123
Exercises 129
Chapter 4. Composite Data Types and Operations 132
4.1 Arrays 133
4.2 Unconstrained Arrays 145
4.3 Array Operations and Referencing 150
4.4 Records 154
Exercises 159
Chapter 5. Digital Modeling Constructs 162
5.1 Entity Declarations 163
5.2 Architecture Bodies 165
5.3 Digital Behavioral Descriptions 168
5.4 Digital Structural Descriptions 197
Exercises 206
Chapter 6. Analog Modeling Constructs 214
6.1 Free Quantities 215
6.2 Terminals and Branch Quantities 219
6.3 Attributes of Terminals and Quantities 228
6.4 Simultaneous Statements 244
6.5 Analog Structural Descriptions 255
6.6 Discontinuities and Break Statements 259
6.7 Step Limit Specifications 271
6.8 Mixed-Signal Descriptions 274
6.9 Mixed-Technology Descriptions 280
Exercises 283
Chapter 7. Design Processing 288
7.1 Analysis 289
7.2 Elaboration 296
7.3 Execution 304
Exercises 307
Chapter 8. Case Study 1: Mixed-Signal Focus 308
8.1 System Overview 309
8.2 Command and Control System Design 309
8.3 Design Trade-Off Analysis 321
Exercises 326
Chapter 9. Subprograms 330
9.1 Procedures 331
9.2 Procedure Parameters 337
9.3 Concurrent Procedure Call Statements 349
9.4 Functions 352
9.5 Simultaneous Procedural Statements 360
9.6 Overloading 365
9.7 Visibility of Declarations 368
Exercises 372
Chapter 10. Packages and Use Clauses 376
10.1 Package Declarations 377
10.2 Package Bodies 385
10.3 Use Clauses 387
10.4 The Predefined Package Standard 390
10.5 IEEE Standard Packages 391
Exercises 402
Chapter 11. Aliases 404
11.1 Aliases for Data Objects 405
11.2 Aliases for Non-Data Items 410
Exercises 413
Chapter 12. Generic Constants 416
12.1 Parameterizing Behavior 417
12.2 Parameterizing Structure 421
Exercises 425
Chapter 13. Frequency and Transfer Function Modeling 428
13.1 Frequency-Based Modeling 429
13.2 Noise Modeling 436
13.3 Laplace Transfer Functions 439
13.4 Discrete Transfer Functions and Sampling 450
Exercises 460
Chapter 14. Case Study 2: Mixed-Technology Focus 464
14.1 Rudder System Overview 465
14.2 S-Domain Implementation 467
14.3 Mixed Mechanical/S-Domain Implementation 481
14.4 Design Trade-Off Analysis 488
Exercises 494
Chapter 15. Resolved Signals 496
15.1 Basic Resolved Signals 497
15.2 IEEE Std_Logic_1164 Resolved Subtypes 506
15.3 Resolved Signals and Ports 508
15.4 Resolved Signal Parameters 512
Exercises 514
Chapter 16. Components and Configurations 520
16.1 Components 521
16.2 Configuring Component Instances 525
16.3 Configuration Specifications 541
Exercises 548
Chapter 17. Generate Statements 556
17.1 Generating Iterative Structures 557
17.2 Conditionally Generating Structures 563
17.3 Configuration of Generate Statements 570
Exercises 576
Chapter 18. Case Study 3: DC-DC Power Converter 584
18.1 Buck Converter Theory and Design 585
18.2 Modeling with VHDL-AMS 592
18.3 Voltage-Mode Control 595
18.4 Averaged Model 596
18.5 Closing the Loop 598
18.6 Design Trade-Off Study 605
Exercises 609
Chapter 19. Guards and Blocks 612
19.1 Guarded Signals and Disconnection 613
19.2 Blocks and Guarded Signal Assignment 622
19.3 Using Blocks for Structural Modularity 628
Exercises 635
Chapter 20. Access Types and Abstract Data Types 640
20.1 Access Types 641
20.2 Linked Data Structures 647
20.3 Abstract Data Types Using Packages 653
Exercises 667
Chapter 21. Files and Input/Output 670
21.1 Files 671
21.2 The Package Textio 710
Exercises 694
Chapter 22. Attributes and Groups 698
22.1 Predefined Attributes 699
22.2 User-Defined Attributes 710
22.3 Groups 723
Exercises 726
Chapter 23. Case Study 4: Communication System 730
23.1 Communication System Overview 731
23.2 Frequency Shift Keying 732
23.3 FSK Detection 735
23.4 Trade-Off Study 741
Exercises 743
Chapter 24. Miscellaneous Topics 746
24.1 Buffer and Linkage Ports 747
24.2 Conversion Functions in Association Lists 749
24.3 Postponed Processes 754
24.4 Shared Variables 757
Exercises 758
Chapter 25. Integrated System Modeling 762
25.1 Top-down Design 763
25.2 System Specification 765
25.3 Partitioning the System 766
25.4 Refining the Design 767
25.5 Model Calibration 769
25.6 System Verification 771
25.7 Synthesis and Reuse 772
25.8 Design Trade-Offs and Optimization 773
Exercises 776
Chapter 26. Case Study 5: RC Airplane System 778
26.1 RC System Overview 779
26.2 Interfacing Command and Control to the Rudder System 779
26.3 System Power Supply Effects 781
26.4 Propeller System 789
26.5 Human Controller 797
26.6 Summary 800
Exercises 801
Appendix A: Using SPICE Models in VHDL-AMS 804
A.1 SystemVision/ADMS (Mentor Graphics Corporation) 804
A.2 VeriasHDL (Synopsys, Inc.) 807
A.3 Auriga (FTL Systems, Inc.) 809
Appendix B: The Predef'med Package Standard 812
Appendix C: IEEE Standard Packages 816
C.1 Std_Logic_l164 Multivalue Logic System 816
C.2 Standard 1076.2 VHDL Mathematical Packages 819
Appendix D: Related Standards 824
D.1 IEEE VHDL Standards 824
D.2 Other Design Automation Standards 828
Appendix E: VHDL-AMS Syntax 834
E.1 Design File 836
E.2 Library Unit Declarations 836
E.3 Declarations and Specifications 838
E.4 Type Definitions 840
E.5 Concurrent Statements 841
E.6 Simultaneous Statements 843
E.7 Sequential Statements 844
E.8 Interfaces and Associations 846
E.9 Expressions 846
Appendix F: Answers to Exercises 848
Appendix G: CD-ROM Guide 878
References 880
Index 884