Efficient Test Methodologies for High-Speed Serial Links (eBook)

Efficient Test Methodologiesfor High-Speed Serial Links 1
1 Introduction 11
1.1 Overview of High-Speed Serial Links 11
1.1.1 High-Speed Serial Link System 11
1.1.2 Testing High-Speed Serial Links 12
1.2 Challenges in Testing High-Speed Serial Links 13
1.3 Contributions of the Dissertation 14
2 An Efficient Jitter Measurement Technique 16
2.1 Comparator Undersampling Technique 16
2.2 Random Jitter Measurement 18
2.2.1 Proposed RJ Measurement Technique 19
2.2.2 Limitations of the Technique 21
2.3 Experimental Results 22
2.3.1 Simulation Results 23
2.3.1.1 Simulation: Case 1 23
2.3.1.2 Simulation: Case 2 23
2.3.1.3 Simulation: Case 3 24
2.3.2 Measurement Results 25
2.3.2.1 Experiment: Case 1 25
2.3.2.2 Experiment: Case 2 26
2.4 Summary 27
3 BER Estimation for Linear Clock and Data Recovery Circuit 28
3.1 BER Analysis with Random Jitter 29
3.1.1 Error Occurrences 29
3.1.2 BER Estimation with Random Jitter 29
3.2 BER Analysis with Random Jitter and Periodic Jitter 31
3.2.1 Jitter Transfer Characteristics of a CDR Circuit 32
3.2.2 BER Estimation with RJ and PJ 34
3.2.2.1 Dual-Dirac Model and Its Modification 34
3.2.2.2 BER Estimation Taking into Account Clock Recovery Function 35
3.3 BER Analysis Including Intrinsic Noise in the CDR Circuit 41
3.4 Experimental Results 43
3.4.1 Simulation Results 43
3.4.2 Hardware Validation Results 44
3.4.2.1 Jitter Transfer Characteristics 45
3.4.2.2 BER Measurement Results 47
3.5 Summary and Future Work 49
4 BER Estimation for Non-linear Clock and Data Recovery Circuit 50
4.1 Jitter Analysis for BB CDR Circuits 50
4.1.1 Jitter Transfer Analysis 51
4.1.2 Jitter Tolerance Analysis 54
4.2 BER Estimation 54
4.2.1 Variation of Jitter Transfer Due to RJ 55
4.2.2 BER Estimation 57
4.3 Experimental Setup and Results 58
4.3.1 Simulation Setup 58
4.3.2 Simulation Results 59
4.4 Summary 60
5 Gaps in Timing Margining Test 61
5.1 Timing Margining Test Basics 61
5.2 Gap Analysis in Timing Margining Test 62
5.2.1 Random Jitter 63
5.2.2 PLL-Based Clock Recovery with Non-linear Phase Detector 64
5.2.3 Jitter Amplification 67
5.2.4 Duty Cycle Distortion in Clock 69
5.3 Summary and Future Work 71
6 An Accurate Jitter Estimation Technique 73
6.1 Characteristics of DJ 73
6.1.1 ISI-Induced Jitter 74
6.1.2 Crosstalk-Induced Jitter 74
6.2 Total Jitter Estimation 76
6.2.1 Estimation Based on Dual-Dirac Model 76
6.2.2 High-Order Polynomial Fitting 79
6.2.3 Accuracy Versus Number of Samples for Fitting 79
6.3 Summary 80
7 A Two-Tone Test Method for Continuous-Time Adaptive Equalizers 82
7.1 Continuous-Time Adaptive Equalizer 83
7.2 Proposed Two-Tone Test Method 85
7.2.1 Description of the Test Method 85
7.2.2 Implementation of the Test Method 86
7.3 Experimental Results 89
7.3.1 MATLAB Simulation Results 89
7.3.2 Transistor-Level Simulation Results 91
7.4 Summary and Future Work 92
8 Conclusions 95
A Extracting Effective PJ and RJ Components from Jitter Histogram 97
References 100