CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
Process-Aware SRAM Design and Test
Seiten
2010
|
Softcover reprint of hardcover 1st ed. 2008
Springer (Verlag)
978-90-481-7855-1 (ISBN)
Springer (Verlag)
978-90-481-7855-1 (ISBN)
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.
Prof. Sachdev has authored several successful books with Springer
and Motivation.- SRAM Circuit Design and Operation.- SRAM Cell Stability: Definition, Modeling and Testing.- Traditional SRAM Fault Models and Test Practices.- Techniques for Detection of SRAM Cells with Stability Faults.- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques.
Reihe/Serie | Frontiers in Electronic Testing ; 40 |
---|---|
Zusatzinfo | XVI, 194 p. |
Verlagsort | Dordrecht |
Sprache | englisch |
Maße | 155 x 235 mm |
Themenwelt | Mathematik / Informatik ► Informatik ► Theorie / Studium |
Informatik ► Weitere Themen ► Hardware | |
Technik ► Elektrotechnik / Energietechnik | |
ISBN-10 | 90-481-7855-X / 904817855X |
ISBN-13 | 978-90-481-7855-1 / 9789048178551 |
Zustand | Neuware |
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