VLSI Circuit Technologies

2.1 INTRODUCTION

There are two classes of silicon devices: bipolar and unipolar transistors. They differ in that both majority and minority carriers participate in the bipolar transistor action while only minority carriers participate in the unipolar transistor. The main bipolar circuit techniques are ECL/CML (emitter-coupled logic/current mode logic), I2L (integrated injection logic), and TTL (transistor-transistor logic). These circuit techniques are for various reasons not suitable for large integrated circuits.

There are several types of unipolar devices, e.g., MOS (metal oxide semiconductor) transistor, JFET (junction field-effect transistor), and MESFET (metal-semiconductor field-effect transistor). In practice only MOS transistors; are used for VLSI circuits. The main unipolar circuit technique is CMOS (complementary metal oxide semiconductor) circuits, but numerous alternatives exist [2, 23–26]. CMOS circuits are often augmented with a few bipolar devices, so-called BiCMOS, to achieve higher speed in critical parts.

Gallium arsenide (GaAs)–based VLSI circuits have recently become available. They are important because of their high speed and compatibility with optical components, for example, lasers. GaAs-based circuits are therefore interesting candidates for many DSP applications. However, there is a widespread consensus that no other technology will effectively compete with CMOS and BiCMOS for several years to come.

2.2 MOS TRANSISTORS

There are two basic types of MOS devices: n-channel and p-channel transistors. Figure 2.1 illustrates the structure of an MOS transistor [10, 12, 14, 15, 21]. An n-channel (nMOS) transistor has two islands of n-type diffusion embedded in a substrate of p-type. A thin layer of silicon dioxide (SiO2) is formed on top of the surface between these islands. The gate is formed by depositing a conducting material on the top of this layer. The gate was made of metal in now outdated technologies, a fact that explains the name of the device (metal oxide semiconductor transistor). Modern MOS processes use polysilicon for the gate. In the nMOS transistor the channel is formed under the gate when proper voltages are applied to the terminals. The free charges in an nMOS device are electrons. The p-channel (pMOS) transistor is similar to the nMOS type except that the substrate is made of n-type silicon and the diffused islands are made of p-type silicon. The free charges in a pMOS device are holes.

A practical circuit has both n- and p-devices that are isolated from each other by so-called wells. Some CMOS processes have both an n-well and a p-well for the p- and n-devices, respectively. Other processes use only a p- or n-type of well in which n- (p-) channel devices are created while p- (n-) channel devices are created directly in thesubstrate.

The dimensions are successively being reduced with the progress of the process technology [14, 15, 19, 25]. It is common practice to characterize a CMOS process by the minimum feature size. As of 1998, the minimum feature size is in the range 0.25 to 0.35 μm. Figure 2.2 shows the geometric layout of a minimum-size transistor with achannel length of 0.8 μm. Notice that there is a difference between the drawn dimension (masks) and the effective dimension that depends on the process [7, 16].

The drawn width of the transistor is 2.0 μm. For Minimum-size transistors in a typical 0.8 μm CMOS technology we have

neff=Wdrawn−2·0.58μm=0.84μmLneff=Ldrawn=0.8μm

and

peff=Wdrawn−2·0.33μm=1.34μmLpeff=Ldrawn+2·0.08μm=0.98μm

The MOS transistor is a four-terminal device: source, gate, drain, and substrate (well). The source of a transistor is defined so that the charges in the channel move from the source toward the drain. For example, for an n-channel transistor the moving charges are electrons. Here, the source is the terminal that has the lowest potential. The terminal with the highest potential is the source for a p-channel transistor since the moving charges are holes.

Schematic circuit symbols are shown for n- and p-channel transistors in Figure 2.3. The type of substrate is often indicated by an arrow, pointing away from the transistor (right) for an n-doped substrate (i.e., for a p-channel transistor) and toward the transistor (left) for an n-channel transistor. Generally, the substrate (well) of the nMOS deviceis grounded and the substrate (well) of the pMOS device is connected to the positivepower supply rail in a digital circuit.

Four different types of devices are possible using MOS technology: n-channel or p-channel transistors that can be either of enhancement mode or depletion mode type. An enhancement mode transistor does not conduct for zero gate-source voltage while a depletion mode transistor does conduct.

The n-channel enhancement mode transistor will conduct and effectively short-circuit the drain and source if a sufficiently large gate-source voltage is applied, but it will not conduct if the gate-source voltage is less than the threshold voltage. A simple model for the transistor is a voltage-controlled switch that is on if the input voltage is high, and off if it is low. The p-channel transistor will conduct if the gate-source voltage is larger than the threshold voltage.

2.2.1 A Simple Transistor Model

Transistors are characterized by a plot of drain current, ID, versus the drainsource voltage, VDS for different values of gate-source voltage, VGS [2, 19, 22–25]. All voltages are referenced with respect to the source voltage. The source and substrate are assumed to be connected. Characteristic curves are shown in Figures. 2.4 and 2.5 for a n- and p-channel transistors, respectively.

The two diagrams show typical device characteristics for a 0.8-μm CMOS technology. Large parameter variations occur in practice among devices on different dies while the variations are somewhat smaller between devices on the same die. The diagrams show that drain-source current flows only when the magnitude of the gate-source voltage exceeds a minimum value, called the threshold voltage, VT, i.e., | VGS | > | VT |. This is more clearly illustrated in Figure 2.6 which depicts the IDn  −VGS characteristics for a fixed VDS.

The threshold voltage is adjusted by implanting ions into the substrate in the region below the gate. Typical values for a 5 V CMOS process are VTn ≈ 0.84 V for an nMOS transistor and VTp ≈ − 0.73 V for a pMOS transistor. The magnitude of the threshold voltage increases with the source-bulk voltage. The bulk is either the substrate or a well in which the transistor is embedded. Typically, VTn ≈ 0.84 V at VDS = 0 and VTn ≈ 1.7 V at VDS = 5 V.

The diagrams shown in Figures. 2.4 and 2.5 can be divided into two regions. The region to the left of this curve is called the linear region. The region where ID remains practically constant (almost independent of VDS) is called the saturation region.

The drain current1, ID for an nMOS transistor can be modeled by:

Dn=0VGS−VTn<0cutoffβnVGS−VTn−VDS2VDSVGS−VTn>VDSlinearβn2VGS−VTn2VGS−VTn<VDSsaturated

where βn = μnεW/(ToxL), μn is the average mobility of the charge carriers (electrons for n-channel and holes for p-channel devices), ε is the permittivity of the SiO2, and Tox is the thickness of the gate oxide.

If the drain-source voltage is increased beyond VDSsat = VGS − VTn the effective length of the channel is reduced. This effect is referred to as channel-length modulation. In order to account for the increase in IDn, Equation (2.1c) is multiplied by a factor [1 + α...