Centered around three design case studies, DSP Integrated Circuits thoroughly details a high-performance FFT processor, a 2-D Discrete Cosine Transform for HDTV, and a wave digital filter for interpolation of the sampling frequency. The case studies cover the essential parts of the design process in a top-down manner, from specification of algorithm design and optimization, scheduling of operations, synthesis of optimal architectures, realization of processing elements, to the floor-planning of the integrated circuit.
* Details the theory and design of digital filters - particularly wave digital filters, multi-rate digital filters, fast Fourier transforms (FFT's), and discrete cosine transforms (DCT's)
* Follows three complete real-world case studies throughout the book
* Provides complete coverage of finite word length effects in DSP algorithms
* In-depth survey of the computational properties of DSP algorithms and their mapping to optimal architectures
* Outlines DSP architectures and parallel, bit-serial, and distributed arithmetic
* Presents the design process in a top-down manner and incorporates numerous problems and solutions
DSP Integrated Circuits establishes the essential interface between theory of digital signal processing algorithms and their implementation in full-custom CMOS technology. With an emphasis on techniques for co-design of DSP algorithms and hardware in order to achieve high performance in terms of throughput, low power consumption, and design effort, this book provides the professional engineer, researcher, and student with a firm foundation in the theoretical as well as the practical aspects of designing high performance DSP integrated circuits. Centered around three design case studies, DSP Integrated Circuits thoroughly details a high-performance FFT processor, a 2-D Discrete Cosine Transform for HDTV, and a wave digital filter for interpolation of the sampling frequency. The case studies cover the essential parts of the design process in a top-down manner, from specification of algorithm design and optimization, scheduling of operations, synthesis of optimal architectures, realization of processing elements, to the floor-planning of the integrated circuit. Details the theory and design of digital filters - particularly wave digital filters, multi-rate digital filters, fast Fourier transforms (FFT's), and discrete cosine transforms (DCT's) Follows three complete "e;real-world"e; case studies throughout the book Provides complete coverage of finite word length effects in DSP algorithms In-depth survey of the computational properties of DSP algorithms and their mapping to optimal architectures Outlines DSP architectures and parallel, bit-serial, and distributed arithmetic Presents the design process in a top-down manner and incorporates numerous problems and solutions
Front Cover 1
DSP INTEGRATED CIRCUITS 2
Copyright Page 3
CONTENTS 4
Chapter 1. DSP Integrated Circuits 16
1.1 Introduction 16
1.2 Digital Signal Processing 17
1.3 Standard Digital Signal Processors 17
1.4 Application-Specific ICs for DSP 19
1.5 DSP Systems 22
1.6 DSP System Design 25
1.7 Integrated Circuit Design 40
Chapter 2. VLSI Circuit Technologies 46
2.1 Introduction 46
2.2 MOS Transistors 46
2.3 MOS Logic 51
2.4 VLSI Process Technologies 63
2.5 Trends in CMOS Technologies 68
Chapter 3. Digital Signal Processing 74
3.1 Introduction 74
3.2 Digital Signal Processing 75
3.3 Signals 76
3.4 The Fourier Transform 77
3.5 The z-Transform 79
3.6 Sampling of Analog Signals 80
3.7 Selection of Sample Frequency 82
3.8 Signal Processing Systems 84
3.9 Difference Equations 87
3.10 Frequency Response 88
3.11 Transfer Function 93
3.12 Signal-Flow Graphs 94
3.13 Filter Structures 95
3.14 Adaptive DSP Algorithms 97
3.15 DFT—The Discrete Fourier Transform 101
3.16 FFT—The Fast Fourier Transform Algorithm 102
3.17 FFT Processor—Case Study 1 111
3.18 Image Coding 113
3.19 Discrete Cosine Transforms 114
3.20 DCT Processor—Case Study 2 120
Chapter 4. Digital Filters 130
4.1 Introduction 130
4.2 FIR Filters 130
4.3 Fir Filter Structures 137
4.4 FIR Chips 141
4.5 IIR Filters 142
4.6 Specification of IIR Filters 143
4.7 Direct Design in the z-Plane 145
4.8 Mapping of Analog Transfer Functions 145
4.9 Mapping of Analog Filter Structures 152
4.10 Wave Digital Filters 153
4.11 Reference Filters 153
4.12 Wave Descriptions 155
4.13 Transmission Lines 156
4.14 Transmission Line Filters 158
4.15 Wave-Flow Building Blocks 159
4.16 Design of Wave Digital Filters 165
4.17 Ladder Wave Digital Filters 168
4.18 Lattice Wave Digital Filters 169
4.19 Bireciprocal Lattice Wave Digital Filters 177
4.20 Multirate Systems 181
4.21 Interpolation With an Integer Factor L 181
4.22 Decimation With A Factor M 189
4.23 Sampling Rate Change With a Ratio L/M 191
4.24 Multirate Filters 192
4.25 Interpolator—Case Study 3 192
Chapter 5. Finite Word Length Effects 202
5.1 Introduction 202
5.2 Parasitic Oscillations 203
5.3 Stability 210
5.4 Quantization In WDFs 210
5.5 Scaling of Signal Levels 213
5.6 Round-Off Noise 222
5.7 Measuring Round-Off Noise 228
5.8 Coefficient Sensitivity 230
5.9 Sensitivity and Noise 231
5.10 Interpolator, Cont. 233
5.11 FFT Processor, Cont. 233
5.12 DCT Processor, Cont. 233
Chapter 6. DSP Algorithms 240
6.1 Introduction 240
6.2 DSP Systems 240
6.3 Precedence Graphs 244
6.4 SFGs in Precedence Form 249
6.5 Difference Equations 254
6.6 Computation Graphs 258
6.7 Equivalence Transformations 262
6.8 Interleaving and Pipelining 268
6.9 Algorithm Transformations 276
6.10 Interpolator, Cont. 282
Chapter 7. DSP System Design 292
7.1 Introduction 292
7.2 A Direct Mapping Technique 293
7.3 FFT Processor, Cont. 296
7.4 Scheduling 307
7.5 Scheduling Formulations 308
7.6 Scheduling Algorithms 328
7.7 FFT Processor, Cont. 338
7.8 Resource Allocation 343
7.9 Resource Assignment 346
7.10 Interpolator, Cont. 349
7.11 FFT Processor, Cont. 356
7.12 DCT Processor, Cont. 363
Chapter 8. DSP Architectures 372
8.1 Introduction 372
8.2 DSP System Architectures 372
8.3 Standard DSP Architectures 374
8.4 Ideal DSP Architectures 380
8.5 Multiprocessors And Multicomputers 385
8.6 Message-Based Architectures 386
8.7 Systolic Arrays 389
8.8 Wave Front Arrays 391
8.9 Shared-Memory Architectures 394
Chapter 9. Synthesis of DSP Architectures 402
9.1 Introduction 402
9.2 Mapping of DSP Algorithms onto Hardware 403
9.3 Uniprocessor Architectures 404
9.4 Isomorphic Mapping of SFGs 409
9.5 Implementations Based on Complex PEs 412
9.6 Shared-Memory Architectures with Bit-Serial PEs 419
9.7 Building Large DSP Systems 425
9.8 Interpolator, Cont. 428
9.9 FFT Processor, Cont. 428
9.10 DCT Processor, Cont. 440
9.11 SIC (Single-Instruction Computer) 441
Chapter 10. Digital Systems 452
10.1 Introduction 452
10.2 Combinational Networks 453
10.3 Sequential Networks 454
10.4 Storege Elements 455
10.5 Clocking of Synchronous Systems 459
10.6 Asynchronous Systems 465
10.7 Finite State Machines (FSMs) 468
Chapter 11. Processing Elements 476
11.1 Introduction 476
11.2 Conventional Number Systems 476
11.3 Redundant Number Systems 482
11.4 Residue Number Systems 485
11.5 Bit-Parallel Arithmetic 487
11.6 Bit-Serial Arithmetic 496
11.7 Bit-Serial Two-Port Adaptor 501
11.8 S/P Multipliers with Fixed Coefficients 504
11.9 Minimum Number of Basic Operations 506
11.10 Bit-Serial Squarers 511
11.11 Serial/Serial Multipliers 515
11.12 Digit-Serial Arithmetic 517
11.13 The CORDIC Algorithm 517
11.14 Distributed Arithmetic 518
11.15 The Basic Shift-Accumulator 522
11.16 Reducing the Memory Size 525
11.17 Complex Multipliers 527
11.18 Improved Shift-Accumulator 529
11.19 FFT Processor, Cont. 531
11.20 DCT Processor, Cont. 537
Chapter 12. Integrated Circuit Design 546
12.1 Introduction 546
12.2 Layout of VLSI Circuits 546
12.3 Layout Styles 552
12.4 FFT Processor, Cont. 560
12.5 DCT Processor, Cont. 562
12.6 Interpolator, Cont. 563
12.7 Economic Aspects 566
Index 570
VLSI Circuit Technologies
2.1 INTRODUCTION
There are two classes of silicon devices: bipolar and unipolar transistors. They differ in that both majority and minority carriers participate in the bipolar transistor action while only minority carriers participate in the unipolar transistor. The main bipolar circuit techniques are ECL/CML (emitter-coupled logic/current mode logic), I2L (integrated injection logic), and TTL (transistor-transistor logic). These circuit techniques are for various reasons not suitable for large integrated circuits.
There are several types of unipolar devices, e.g., MOS (metal oxide semiconductor) transistor, JFET (junction field-effect transistor), and MESFET (metal-semiconductor field-effect transistor). In practice only MOS transistors; are used for VLSI circuits. The main unipolar circuit technique is CMOS (complementary metal oxide semiconductor) circuits, but numerous alternatives exist [2, 23–26]. CMOS circuits are often augmented with a few bipolar devices, so-called BiCMOS, to achieve higher speed in critical parts.
Gallium arsenide (GaAs)–based VLSI circuits have recently become available. They are important because of their high speed and compatibility with optical components, for example, lasers. GaAs-based circuits are therefore interesting candidates for many DSP applications. However, there is a widespread consensus that no other technology will effectively compete with CMOS and BiCMOS for several years to come.
2.2 MOS TRANSISTORS
There are two basic types of MOS devices: n-channel and p-channel transistors. Figure 2.1 illustrates the structure of an MOS transistor [10, 12, 14, 15, 21]. An n-channel (nMOS) transistor has two islands of n-type diffusion embedded in a substrate of p-type. A thin layer of silicon dioxide (SiO2) is formed on top of the surface between these islands. The gate is formed by depositing a conducting material on the top of this layer. The gate was made of metal in now outdated technologies, a fact that explains the name of the device (metal oxide semiconductor transistor). Modern MOS processes use polysilicon for the gate. In the nMOS transistor the channel is formed under the gate when proper voltages are applied to the terminals. The free charges in an nMOS device are electrons. The p-channel (pMOS) transistor is similar to the nMOS type except that the substrate is made of n-type silicon and the diffused islands are made of p-type silicon. The free charges in a pMOS device are holes.
A practical circuit has both n- and p-devices that are isolated from each other by so-called wells. Some CMOS processes have both an n-well and a p-well for the p- and n-devices, respectively. Other processes use only a p- or n-type of well in which n- (p-) channel devices are created while p- (n-) channel devices are created directly in thesubstrate.
The dimensions are successively being reduced with the progress of the process technology [14, 15, 19, 25]. It is common practice to characterize a CMOS process by the minimum feature size. As of 1998, the minimum feature size is in the range 0.25 to 0.35 μm. Figure 2.2 shows the geometric layout of a minimum-size transistor with achannel length of 0.8 μm. Notice that there is a difference between the drawn dimension (masks) and the effective dimension that depends on the process [7, 16].
The drawn width of the transistor is 2.0 μm. For Minimum-size transistors in a typical 0.8 μm CMOS technology we have
neff=Wdrawn−2·0.58μm=0.84μmLneff=Ldrawn=0.8μm
and
peff=Wdrawn−2·0.33μm=1.34μmLpeff=Ldrawn+2·0.08μm=0.98μm
The MOS transistor is a four-terminal device: source, gate, drain, and substrate (well). The source of a transistor is defined so that the charges in the channel move from the source toward the drain. For example, for an n-channel transistor the moving charges are electrons. Here, the source is the terminal that has the lowest potential. The terminal with the highest potential is the source for a p-channel transistor since the moving charges are holes.
Schematic circuit symbols are shown for n- and p-channel transistors in Figure 2.3. The type of substrate is often indicated by an arrow, pointing away from the transistor (right) for an n-doped substrate (i.e., for a p-channel transistor) and toward the transistor (left) for an n-channel transistor. Generally, the substrate (well) of the nMOS deviceis grounded and the substrate (well) of the pMOS device is connected to the positivepower supply rail in a digital circuit.
Four different types of devices are possible using MOS technology: n-channel or p-channel transistors that can be either of enhancement mode or depletion mode type. An enhancement mode transistor does not conduct for zero gate-source voltage while a depletion mode transistor does conduct.
The n-channel enhancement mode transistor will conduct and effectively short-circuit the drain and source if a sufficiently large gate-source voltage is applied, but it will not conduct if the gate-source voltage is less than the threshold voltage. A simple model for the transistor is a voltage-controlled switch that is on if the input voltage is high, and off if it is low. The p-channel transistor will conduct if the gate-source voltage is larger than the threshold voltage.
2.2.1 A Simple Transistor Model
Transistors are characterized by a plot of drain current, ID, versus the drainsource voltage, VDS for different values of gate-source voltage, VGS [2, 19, 22–25]. All voltages are referenced with respect to the source voltage. The source and substrate are assumed to be connected. Characteristic curves are shown in Figures. 2.4 and 2.5 for a n- and p-channel transistors, respectively.
The two diagrams show typical device characteristics for a 0.8-μm CMOS technology. Large parameter variations occur in practice among devices on different dies while the variations are somewhat smaller between devices on the same die. The diagrams show that drain-source current flows only when the magnitude of the gate-source voltage exceeds a minimum value, called the threshold voltage, VT, i.e., | VGS | > | VT |. This is more clearly illustrated in Figure 2.6 which depicts the IDn −VGS characteristics for a fixed VDS.
The threshold voltage is adjusted by implanting ions into the substrate in the region below the gate. Typical values for a 5 V CMOS process are VTn ≈ 0.84 V for an nMOS transistor and VTp ≈ − 0.73 V for a pMOS transistor. The magnitude of the threshold voltage increases with the source-bulk voltage. The bulk is either the substrate or a well in which the transistor is embedded. Typically, VTn ≈ 0.84 V at VDS = 0 and VTn ≈ 1.7 V at VDS = 5 V.
The diagrams shown in Figures. 2.4 and 2.5 can be divided into two regions. The region to the left of this curve is called the linear region. The region where ID remains practically constant (almost independent of VDS) is called the saturation region.
The drain current1, ID for an nMOS transistor can be modeled by:
Dn=0VGS−VTn<0cutoffβnVGS−VTn−VDS2VDSVGS−VTn>VDSlinearβn2VGS−VTn2VGS−VTn<VDSsaturated
(2.1a, 2.1b, 2.1c)
where βn = μnεW/(ToxL), μn is the average mobility of the charge carriers (electrons for n-channel and holes for p-channel devices), ε is the permittivity of the SiO2, and Tox is the thickness of the gate oxide.
If the drain-source voltage is increased beyond VDSsat = VGS − VTn the effective length of the channel is reduced. This effect is referred to as channel-length modulation. In order to account for the increase in IDn, Equation (2.1c) is multiplied by a factor [1 + α...
Erscheint lt. Verlag | 24.2.1999 |
---|---|
Sprache | englisch |
Themenwelt | Kunst / Musik / Theater ► Design / Innenarchitektur / Mode |
Informatik ► Grafik / Design ► Digitale Bildverarbeitung | |
Technik ► Elektrotechnik / Energietechnik | |
ISBN-10 | 0-08-050477-9 / 0080504779 |
ISBN-13 | 978-0-08-050477-3 / 9780080504773 |
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