Energy Scalable Radio Design (eBook)

Preface 7
Table of contents 8
1 Introduction and Motivation 13
Dreaming of a Smart Environment 13
Limited Energy Resources and the Energy Gap 13
Strategies to Bridge the Energy Gap 15
Power- and Energy-Oriented System-to-Circuit Design 15
Power Analysis and Optimization at Design Time 16
Energy Analysis and Optimization at Design Time 16
Energy-Efficient Wireless Communication and IR-UWB 18
Energy-per-Useful-Bit 18
Impulse Radio UltraWideband Communication 19
Runtime Energy Scalability 20
Book Scope and Organizational Overview 22
2 Adaptation of Classical Design Flow for Energy-Driven System-to-CircuitDesign 24
Introduction 24
Classical (Digital) Top–Down Design Flow: Gajski–Kuhn 25
Moore's Law and the Design Productivity Gap 25
Design Abstraction, Methodology and Reuse to Close the Gap 26
Gajski–Kuhn Y chart 27
Need for Energy-Driven CrossLayer Scalable System-to-Circuit Design 30
Need for Energy-Driven Design 30
Need for CrossLayer Design 31
Need for Design Towards Scalability 33
Need for Mixed-Signal System Design 34
Proposed Adaptations of the Classical Design Flow 34
Energy-Oriented Design Objective 34
CrossLayer Design Techniques 35
Use of Bottom–Up Power Estimations 36
Use of Decision Postponement 37
Algorithmic/Architectural-Level DSE 38
Derivation of Optimal Degree of Runtime Flexibility 39
System-Oriented Parameter Selection for Mixed Signal Design 41
Conclusion 42
3 System Level Specifications and Design 43
Introduction 43
System Specifications 43
Target Application Domains 44
Extracted Specifications 45
Selection of the Air Interface 47
Setup of the Comparison Based on EPUB 48
Air Interface Candidates 49
Selection of the Optimal Candidate 51
UWB Communication 53
UWB History and Regulations 53
IR-UWB Basics 55
UWB Advantages 58
Additional UWB-Related Specifications 59
Conclusion 60
4 Algorithmic/Architectural Design Space Exploration 61
Introduction 61
UWB Communication and Receiver Framework 63
Receiver Alternatives 67
FD 67
RAKE and RAKE-Like Reception 68
Averaged Template Reception 69
Partially Analog/Hybrid 69
Digital-To-Analog Converter Based AnalogCorrelation 69
Simplified Analog Correlation 71
Quadrature Analog Correlation 72
Transmitted Reference 74
Energy Detector 75
Flashing Receiver 75
Fully Analog 76
Receiver Summary 76
Receiver Comparison: Power, Performance, EPUB 76
Performance Simulation 76
Theoretical Derivation 76
Simulation Setup 79
Simulation Results 80
Power Estimation 81
Minimal EPUB 86
A/A DSE Summary 87
Further Considerations 90
Packet Length 90
Frequency Band 90
Technology Scaling 92
802.15.4a Compatibility 92
Conclusion 95
5 Algorithmic/Architectural Level Refinement 96
Introduction 96
Algorithm Refinement 96
Data Detection 97
Pulse Recovery 98
Despreading with the PN Code and Data Detection 105
Synchronization During Data Detection 107
Acquisition 110
Acquisition Basic Principles 110
Window and Code Alignment: Strongest Path 110
Window and Code Alignment: MultiPath 121
Effect of CO and Offset Estimation 126
VGA Training 128
End-of-Preamble 128
Ranging 128
Coarse Ranging Based on the Optimal IntegrationWindow 129
Ranging Refinement Based on the Energy Profile 129
Ranging Refinement Based on the Received Phase 130
Architecture Refinement 131
System Architecture 132
Back-End Architecture 133
Front-End Architecture 135
Deriving Front-End Building Block Specifications 135
Conclusion 141
6 Digital RT Level Design: Flexibility to Save Energy 143
Introduction 143
Design Based on Nested FLEXmodules 144
Need for Flexible, Regular, Nested Modules 144
FLEXmodules Offer Flexibility at Low Cost 144
Custom MicroController 145
Chip Architecture Based on FLEXmodules 146
Measuring and Weighing Flexibility 148
Difficulties in Measuring Flexibility 148
Alternative Measure of Flexibility 149
Cost of Flexibility 151
Benefits of Flexibility 153
Energy-Optimal Design Through Flexibility 154
Flexibility of FUs: Parameterized Code Generatorand Correlator 155
Flexibility of FLEXmodules: The ct_pr Unit 160
Intermediate Conclusion on the Flexibility–Power–PerformanceTrade-Off 167
Detailed Back-End Architecture and Design 168
TOP FLEXmodule 168
CLK_GEN FLEXmodule 169
COMM FLEXmodule 169
SE FLEXmodule 171
CT FLEXmodule 171
DD FLEXmodule 182
FIFOs 186
Clock and Power Domains 187
Debug 188
Final Back-End Implementation 189
Flexibility Comparison of the Implemented Design 190
Conclusion 192
7 Chip and System Measurements 193
Introduction 193
Back-End Measurements 193
Measurement Setup 193
Measurement Results 195
Functional Measurements 195
Energy-Efficiency and Flexibility Measurements 199
Back-End Measurement Summary and Possible Improvements 203
System Measurements: 3–5 GHz Band 205
Measurement Motivation 205
Measurement Setup 206
Measurement Setup Problems and Patches 208
Measurement Results 209
Wired Measurements 209
Wireless Measurements 212
3–5 GHz System Measurement Summary 214
System Measurements: 0–960 MHz Band 214
Measurement Setup 214
Measurement Results 216
Wired Measurements 216
Wireless Measurements 218
0–960 MHz System Measurement Summary 219
Receiver Comparison 220
Conclusion 222
Conclusions 225
Bibliography 228
Index 247