Practical Design Verification
Cambridge University Press (Verlag)
978-0-521-85972-1 (ISBN)
Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT).
Diraj K. Pradhan is Chair of Computer Science at the University of Bristol, UK. He previously held the COE Endowed Chair Professorship in Computer Science at Texas A & M University, also serving as Founder of the Laboratory of Computer Systems there. He has also worked as a Staff Engineer at IBM, and served as the Founding CEO of Reliable Computer Technology, Inc. A Fellow of ACM, the IEEE, and the Japan Society of Promotion of Science, Professor Pradhan is the recipient of a Humboldt Prize, Germany, and has numerous major technical publications spanning more than 30 years. Ian G. Harris is Associate Professor in the Department of Computer Science, University of California, Irvine. He is an Executive Committee Member of the IEEE Design Automation Technical Committee (DATC) and Chair of the DATC Embedded Systems Subcommittee, as well as Chair of the IEEE Test Technology Technical Committee (TTTC) and Publicity Chair of the IEEE TTTC Tutorials and Education Group. His research interests involve the testing and validation of hardware and software systems.
1. Model checking and equivalence checking M. Fujita; 2. Transaction level system modeling D. Gajski and S. Abdi; 3. Result checking, monitors and assertions H. Foster; 4. System debugging strategies W. Wolf; 5. Test generation and coverage metrics M. Sonza Reorda, G. Squillero and E. Sanchez; 6. System C and Vera in a verification flow S. Verma and I. G. Harris; 7. Decision diagrams for verification M. Ciesielski, D. K. Pradhan and A. M. Jabir; 8. Boolean satisfiability and EDA applications J. Marques-Silva.
| Erscheint lt. Verlag | 11.6.2009 |
|---|---|
| Verlagsort | Cambridge |
| Sprache | englisch |
| Maße | 177 x 254 mm |
| Gewicht | 720 g |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| ISBN-10 | 0-521-85972-7 / 0521859727 |
| ISBN-13 | 978-0-521-85972-1 / 9780521859721 |
| Zustand | Neuware |
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