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Emerging MOSFET Technologies

Kalyan Biswas1 and Angsuman Sarkar2

1ECE Department, MCKV Institute of Engineering, Liluah, Howrah, West Bengal, India

2ECE Department, Kalyani Govt. Engineering College, Kalyani, Nadia, West Bengal, India

1.1 Introduction: Transistor Action

The human life of the modern generation has been revolutionized by the progress of complementary metal–oxide–semiconductor (CMOS) technology. Metal–oxide–semiconductor field‐effect transistor (MOSFET) is one of the most noteworthy inventions of the twentieth century. One important milestone in the progress of semiconductor integrated circuits was the famous – Moore's law [1]. Following Moore's law, the performance of MOSFET has been improved continuously at an intense rate through gate length scaling. To serve the next‐generation high‐performance requirements with lower operating power, unrelenting scaling of CMOS technology has now reached the atomic scale dimensions. The trend will continue with emerging areas of applications such as the internet of things (IoT), e‐mobility, artificial intelligence, and 5G. The cutting‐edge innovation in MOSFET technologies is the most important and at the heart of these emerging technologies. A schematic diagram of the Conventional Bulk MOSFET Structure is shown in Figure 1.1.

Figure 1.1 Schematic diagram of the Conventional Bulk MOSFET Structure.

1.2 MOSFET Scaling

This downscaling of dimensions of the device is critical to integrate the greater number of devices in integrated circuits (ICs). As a consequence of the Moore's law, every year channel length of the MOSFET sinks, causing short channel effect (SCEs). SCEs are affecting power consumption of the circuits [2–9]. The transistor scaling target has been made reachable because of the advanced lithographic capability to make shorter/thinner channels. In the early stage, scaling was possible with conventional structures and material technology, but it is understood that conventional scaling technology cannot continue forever. Therefore, investigation of non‐classical device structures became necessary.

1.3 Challenges in Scaling the MOSFET

Scaling of MOSFETS is not an easy task but faces lots of challenges. Normally, six different short‐channel effects can be distinguished such as “Sub‐Threshold Slope,” DIBL and threshold voltage roll‐off, velocity saturation, hot carrier effects, and direct source to drain tunneling [10–12].

As the SCEs set hurdles to device operation and degrade device performance, these effects should be removed or minimized, so that a device with a shorter physical channel length can preserve the required device characteristics. Researchers tried to overcome these problems by reducing the gate oxide thickness and the depth of source/drain junction while reducing the gate length in conventional bulk MOSFETs. But these scales reached the physical limit of dimension. As a remedy, gate dielectric materials with higher permittivity were used. The use of these high‐k materials as gate oxide allowed for achieving smaller equivalent oxide thickness with a thicker physical dimension. But shrinking of MOSFET to the sub‐10 nm scale is challenging and new technologies were necessary. As per ITRS forecasts and published literature, it is understood that the main research is going on in two different directions: possible modification of the planar architecture and use of non‐planner 3D structure [13–17] to push for its physical limits, or a new way of making transistors, such as devices based on III–V group materials, use of nanomaterials and nanotechnologies like silicon nanowires, carbon nanotubes (CNTs) or graphene, single electron transistors, and also some other emerging devices such as quantum cellular automata and spin‐based electronics.

1.4 Emerging MOSFET Architectures

For decades, traditional scaling techniques based on sinking its physical dimensions have largely dominated the development path of MOSFETs. However, this traditional scaling technique is not valid for emerging nanoscale devices. As device scaling enters beyond the 22 nm node, various significant changes in terms of device architecture and materials in the traditional MOSFET would be required for the competent operation of the device and to extend Moore's law [18–21]. To surmount SCEs, researchers are employing different strategies for nanoscale devices. The main approaches are (i) by employing different structures such as multigate MOSFETs (ii) advanced device physics approaches, such as junctionless MOSFET, tunnel FET (TFET), and (iii) different channel materials having higher carrier mobility such as III–V‐based materials, strained silicon, CNTs, Graphene, etc. for continuing the progress in nanoscale.

1.4.1 Tunnel FET

To reduce power consumption in MOSFETs without degrading device performance, operating voltage (Vdd) and threshold voltage (Vth) of the device need to be scaled down. If Vth is reduced keeping sub threshold swing (SS) of MOSFET unchanged, the power consumption increases. The TFET, which is based on the principle of band‐to‐band quantum tunneling, is one of the most favorable devices, having a steep slope for applications in low‐power circuits. The device structure of a TFET differs from that of the conventional MOSFET as a type of doping in the source region and drain region of TFET are of opposite types. A schematic diagram of single‐gate n‐type TFET is shown in Figure 1.2. A positive voltage in the gate and reverse bias between the source and drain is required to switch the n‐type device ON. It is a semiconductor device based on the band‐to‐band tunneling principle of electrons rather than thermal emission. TFETs operate by tunneling through the S/D barrier rather than diffusion over the barrier [22–31]. The device switches between ON‐state as well as OFF‐state at lower voltages than the Vdd of the MOSFET, making it a suitable choice for low‐power consumption applications in the era of emerging nanoscale devices. This type of device can provide extremely low OFF‐current and steeper sub‐threshold slope than conventional MOSFET. Tunneling occurs for an electron between the valence band of the semiconductor to the conduction band through a potential barrier without having enough energy required for this transition, and this phenomenon can only be explained by quantum mechanical physics. The output characteristics of a TFET are dependent on the parameters such as the doping, the gate work function, etc. Therefore, these parameters can be modified to obtain the desired output characteristics of a TFET. However, from the fabrication point of view, TFET faces a few challenges such as the fabrication of an ultra‐thin body required for robust electrostatics, formation of abrupt junction, III–V/high‐k interface with low trap density, etc.

Figure 1.2 Schematic diagram of tunnel FET.

Two‐dimensional crystal semiconductors are being investigated as the materials of the channels for field effect transistors (FETs). The main advantages of such 2D‐transistors consist of outstanding electrostatic control of the gate terminal because of the considerably higher surface‐to‐volume ratio, pristine surfaces to confirm better interface quality with the insulators, and greater electrical conductivity owing to the ballistic/quasi‐ballistic transport. It also offers tunable electronic properties dependent on the layer and stacking providing further flexibility in transistor design. These distinctive attributes offer the chance to acquaint with 2D materials in the design of TFET, which can concurrently combine the benefits of greater electrostatic integrity and tunneling barrier engineering. As a result, the arena of TFET design based on 2D materials has grown significantly in recent years.

1.4.2 Nanowire FET

In the era of sub‐10‐nm technology nodes, cylindrical‐shaped structures with gates all around were proposed to provide better gate controllability on the channel and reduce “Short Channel Effects” [32–35]. In this structure, a gate is wrapped around the cylindrical‐shaped channel region and termed a silicon nanowire FET (Figure 1.3). Nanowires can be fabricated with single‐crystal structures, controllable doping, and diameters as small as several nanometers. Though the silicon nanowire transistors (SNWT) improves device performance, the fluctuations in process parameters rigorously affect the device characteristics. As per the projection of the International Technology Roadmap for Semiconductor (ITRS), the multiple‐gate SOI MOSFETs will be able to scale up to sub‐10 nm dimensions and are capable candidates for nanoscale devices in the future.

Figure 1.3 Schematic 3D view and...