1
On Analog Circuits

1.1. Introduction: miscellaneous

1.1.1. SPICE

SPICE (Simulation Program with Integrated Circuit Emphasis) is the standard for simulating analog circuits. Anyone who does not know this does not belong to the fraternity of electronic circuit analogists.

SPICE was created at the University of California (Berkeley) in the early 1970s by Ron Rohrer’s team, including Larry Nagel (see his famous thesis). It later became the standard for analog simulators. Three versions followed one another, including SPICE3, dated 1985.

1.1.1.1. A brief history of SPICE

The need for a circuit simulation program, “smart” people with a vision and hardworking teams of students and professionals have all contributed to the realization and evolution of SPICE. A brief history of this powerful simulator is explained below, which is organized primarily according to the different versions of SPICE.

CANCER

• In the early 1970s, Ron Rohrer hoped to develop a simulation program for his work on optimization at the University of California, Berkeley.
• Rohrer’s students, including Larry Nagel, created CANCER (Computer Analysis of Nonlinear Circuits Excluding Radiation).
• It performs DC, AC, and transient analysis.
• The devices include diodes (Shockely equations) and bipolar junction transistors (Ebers–Moll equations).

Other simulation programs at the time included ECAP (Electronic Circuit Analysis Program) and IBM’s Autonetics TRAC.

SPICE1

• In 1972, Nagel and Pederson launched SPICE1 (Simulation Program with IC Emphasis) in the public domain.
• SPICE became the industry standard simulation tool.
• Bipolar junction transistor models were replaced by Gummel–Poon equations.
• JFET and MOSFET templates were added.
• It was based on nodal analysis.
• It was written in FORTRAN code and runs on large computers.

SPICE2

• Nagel’s 1975 version offered significant improvements.
• Modified nodal analysis (MNA), replacing the old analysis, supported voltage sources and inductors from this point onwards.
• Memory was dynamically allocated to accommodate the increasing size and complexity of circuits.
• It has adjustable simulation of time step control speeds.
• The MOSFET and bipolar models were revised and extended.
• SPICE2G.6 (1983) is the latest version of FORTRAN.

At present, it is still available in Berkeley. Many commercial simulators today are based on SPICE2G.6.

SPICE3

• SPICE code was rewritten in programming language C (1985).
• It has a graphical interface to display the results.
• It included polynomial capacitors, inductors and voltage-controlled sources.
• The new version eliminated many convergence problems.
• Models added were as follows: MESFET, lossy transmission line and nonideal switch.
• Improved semiconductor models adapted to smaller transistor geometries.
• It is not backward compatible with SPICE2.

1980s and beyond

• Published commercial versions include HSPICE, IS_SPICE and MICROCAP.
• MicroSim launched PSPICE, the first PC version of SPICE.
• SPICE attracted many more users in industry and academia.
• EDLO is dedicated to RF.
• HICUM is dedicated to microwaves.
• Companies integrated SPICE versions into their “schematics” entry and layout packages (geometry/pattern).

1.1.1.2. A SPICE program

SPICE is therefore the essential software for studying analog circuits.

1.1.1.3. Program example

The program example is given as follows.

I-V characteristics for SS model of CMOS devices

MODEL NSS NMOS LEVEL =3 RSH=0 TOX=275E-10 LD=0 . 1E-6 XJ=0 . 14E-6

+ CJ=1 . 6E-4 CJSW=1 8E-10 UO550 VTO=1 . 022 CGSO=1 . 3E10

+ CGDO=1 3E-10 NSUB=4E15 NFS=1E10

+ VMAX=12E4 PB=0 . 7 MJ=0 . 5 MJSW=0 . 3 THETA=0 . 06 KAPPA=0 . 4 ETA=0 . 14

. MODEL PSS PMOS LEVEL=3RSH=0 TOX=275E-10 LD=0 . 3E-6 XJ=0 . 42E-6

+ CJ=7 . 7E-4 CJSW=5 . 4E-10 UO=180 VTO=-1 . 046 CGSO=4E-10

+ CGDO=4E-10 TPG=-1 NSUB=7E15 NFS=1E10

+ VMAX=12E4 PB=0 . 7 MJ=0 . 5 MJSW=0 . 3 ETA=0 . 06 THETA=0 . 03 KAPPA=0 . 4

M1 1 10 0 0 NSS W=13 . 2U L=2 . 25U

VDS 20 0

* VGS is positive for nMOS and negative for pMOS

VGS 10 0 5V

* VIDS defines current direction for drain

VIDS 20 1

.DC VDS 0 5 0 . 05

.PRINT DC I (VIDS)

.PLOT DC I (VIDS)

.WIDTH IN=75 OUT=75

.END

Calculation of current-voltage characteristics of .CMOS

Used for the SPICE (Simulation Program with Integrated Circuits Emphasis) simulation program.

* CMOS OPERATIONAL AMPLIFIER *

**** INPUT LISTING   TEMPERATURE = 27.000 DEG C
**************************************************************************
************

.MODEL MP1 PMOS (LEVEL=3 TOX=250E-10 VTO=0 . 55

+ GAMMA=0 . 38 KP=25 . 2E-6 NSUB=2E16 THETA=0 . 163

+VMAX=1E5 FTA=0 DELTA=0 KAPPA=0 . 8 CGSO=0 . 65N CGDO=0 . 65N )

.MODEL MN1 NMOS (LEVEL=3 TOX=250E-10 VTO=0 . 55

+ GAMMA=0 . 1 KP=86 . 8E-6 NSUB=2E16 THETA=0 . 08

+ VMAX=1E5 FTA=0 DELTA=0 KAPPA=0 . 8 CGSO=0 . 42N CGDO= 0 . 42N )

VDD 10 0 DC 5

VSS 11 0 DC -5

CCR 4 5 10P

CCH 5 0 20P

RIN 16 0 1

* AMPLIFIER

VIN 15 0 AC 1

.AC DEC 5 100 100MEG

.PLOT AC VD8 (5) VP (5)

.WIDTH OUT =80

.END

1.1.2. Technologies: conception-aided design

CMOS operational amplifier

Technology

The technology used is as follows:

• passivation: esio2: 0.5 − 1 μm;
• N++: heavily doped buried layer → low resistance;
• P+ zones: insulation wells;
• P+-N junction in reverse → insulation;
• N++ zone: only for “beep”;
• Si3 N4: silicon nitride (mask for implants);
• Si3 N4: prevents oxide growth (but beaks of parasitic birds at the edge of masks: birds peaks).

Below, we shall resume the basic steps of manufacturing the two preferred devices of microelectronics. Diagrams for this have been given in Volume 1.

Bipolar junction transistor

N_epitaxy collector region (0.1–10 Ω.cm):

Opening windows are used to create the base and insulation wells. Opening in the base region is used to create the emitter.

Base: a few

N+: ohmic collector contact

Evaporation of contacts

P-channel MOS:

• thermal oxidation: ;
• P+ implementation for drain.

Reoxidation takes place and then so does photo-etching of the oxide.

Gate oxide (dry O2 for good dielectric quality); thickness: 0.1–0.15 μm.

Field oxide (FOX: Field OXide; LOCOS: LOCal Oxide on Silicon); very thick: 1–1.5 μm.

Self-aligned gate

I2: (ionic implantation) = 80 keV; the oxide lets boron through (a very small atom), but the gate stops it, and therefore serves as a natural mask.

Polysilicon gate NMOS inverter

Fabrication process steps:

• Si3 N4 is impermeable to O2;
• boron: P type;
• LOCOS: Si3 N4;
• Bird beak: SiO2;
• threshold voltage adjustment is expressed as: VTadjust;
• phosphorus → N type.

The I2 of phosphorus creates source and drain zones and, at the same time, dopes the polysilicone.

The polysilicone “embedded” in the oxide makes it possible to manufacture several levels of interconnections.

Self-aligned polysilicon gate

1. Phase 1: Local oxidation:
   1. Thermal growth of a thin layer of silicon oxide.
   2. Engraving according to...