Phase-Locked Loops (eBook)

Woogeun Rhee, PhD, is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He has over 25 years of professional career experience in integrated circuit design with nearly 10 years in industry and 16 years in academia. Dr. Rhee is one of a few researchers who made significant contributions to PLL architectures and circuits not only within different careers (academia and industry) but also over different fields (wireless and wireline systems). He is an IEEE Fellow. Zhiping Yu, PhD, is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He is an IEEE Life Fellow with over 400 published papers on subjects related to ICCAD, nanoelectronics and RF circuit design.

Preface xiii

About Authors xv

1 Introduction 1

1.1 Phase-Lock Technique 1

1.2 Key Properties and Applications 2

1.3 Organization and Scope of the Book 6

Part I Phase-Lock Basics 9

2 Linear Model and Loop Dynamics 11

2.1 Linear Model of the PLL 11

2.2 Feedback System 13

2.3 Loop Dynamics of the PLL 16

2.4 Noise Transfer Function 26

2.5 Charge-Pump PLL 29

2.6 Other Design Considerations 39

3 Transient Response 43

3.1 Linear Transient Performance 44

3.2 Nonlinear Transient Performance 52

3.3 Practical Design Aspects 56

Part II System Perspectives 67

4 Frequency and Spectral Purity 69

4.1 Spur Generation and Modulation 69

4.2 Phase Noise and Random Jitter 87

5 Application Aspects 101

5.1 Frequency Synthesis 102

5.2 Clock-and-Data Recovery 112

5.3 Clock Generation 120

5.4 Synchronization 127

Part III Building Circuits 135

6 PhaseDetector 137

6.1 Non-Memory Phase Detectors 137

6.2 Phase-Frequency Detector 142

6.3 Charge Pump 149

7 Voltage-Controlled Oscillator 165

7.1 Oscillator Basics 166

7.2 LC VCO 175

7.3 RING VCO 190

7.4 Relaxation VCO 201

8 FrequencyDivider 209

8.1 Basic Operation 209

8.2 Circuit Design Considerations 219

8.3 Other Topologies 229

Part IV PLL Architectures 237

9 Fractional-N PLL 239

9.1 Fractional-N Frequency Synthesis 239

9.2 Frequency Synthesis with Delta-Sigma Modulation 249

9.3 Quantization Noise Reduction Methods 271

9.4 Frequency Modulation by Fractional-N PLL 278

10 Digital-Intensive PLL 287

10.1 DPLL with Linear TDC 288

10.2 DPLL with 1-Bit TDC 304

10.3 Hybrid PLL 315

11 Clock-and-Data Recovery PLL 325

11.1 Loop Dynamics Considerations for CDR 325

11.2 CDR PLL Architectures Based on Phase Detection 329

11.3 Frequency Acquisition 340

11.4 DLL-assisted CDR Architectures 344

11.5 Open-Loop CDR Architectures 351

References 355

Index 359