Microwave Circuits in Bulk and Fully-Depleted Silicon-on-Insulator CMOS Technologies

This work presents microwave circuits in 65 nm bulk, and 22 nm fully depleted silicon-on-insulator (FDSOI) complementary metal-oxide-semiconductor (CMOS) technologies. In the first part of the thesis, the work explains the microwave properties of the two state-of-the-art CMOS technologies and gives reasons why CMOS is nowadays attractive for microwave circuit design. The second half shows front-end circuits designed for two research projects.

The first project consists of a quadrature-phase receiver and a high-efficiency transmitter in 65 nm bulk CMOS for a 24 GHz localization system based on the secondary radar principle. The receiver circuitry includes a low-noise amplifier (LNA), poly-phase network, and passive down-converter with post-amplifier. In the LNA, a new method is used, which, despite process tolerances and model uncertainties, maximizes the gain in a target frequency band. The receiver employs a poly-phase network realized by a small directional coupler based on lumped elements. New is here that the coupler omits the termination of the isolated port reducing noise in the receiver. Furthermore, the system uses frequency doubling of the local oscillator (LO) to enable the operation of a digital phase-locked loop (PLL) with low phase noise. Therefore, this work introduces the first truly balanced push-push (PP) frequency doubler, which allows mbesides for high output power, high efficiency, and high suppression of the fundamental wave at the same time.

The second project aims at a broadband receiver, which covers the complete W-band from 75 to 110 GHz for future 100 Gb/s wireless communication. The receiver utilizes a frequency quadrupler to multiply an 18.5/,GHz LO signal for downconversion of the W-band RF frequencies to 1 to 36 GHz intermediate frequencies (IF). The quadrupler cascades two truly balanced PP doublers designed in 22 nm FDSOI CMOS. Furthermore, the PP doublers use a more efficient floorplan, which results in lower chip area consumption.