Introduction to VLSI Design Flow
Cambridge University Press (Verlag)
978-1-009-20081-3 (ISBN)
Chip designing is a complex task that requires an in-depth understanding of VLSI design flow, skills to employ sophisticated design tools, and keeping pace with the bleeding-edge semiconductor technologies. This lucid textbook is focused on fulfilling these requirements for students, as well as a refresher for professionals in the industry. It helps the user develop a holistic view of the design flow through a well-sequenced set of chapters on logic synthesis, verification, physical design, and testing. Illustrations and pictorial representations have been used liberally to simplify the explanation. Additionally, each chapter has a set of activities that can be performed using freely available tools and provide hands-on experience with the design tools. Review questions and problems are given at the end of each chapter to revise the concepts. Recent trends and references are listed at the end of each chapter for further reading.
Sneh Saurabh is Associate Professor at the Department of Electronics and Communication Engineering at the Indraprastha Institute of Information Technology, New Delhi, India. He has rich experience in the semiconductor industry, having spent sixteen years working for industry leaders such as Cadence Design Systems, Synopsys India, and Magma Design Automation. His research interests include VLSI design and automation, nanoelectronics, and energy-efficient systems.
Part I. Overview of VLSI Design Flow: Chapter 1. Foundation; Chapter 2. Introduction to Integrated Circuits; Chapter 3. Pre-RTL Methodologies; Chapter 4. RTL to GDS Implementation Flow; Chapter 5. Verification Techniques; Chapter 6. Testing Techniques; Chapter 7. Post-GDS Processes; Part II. Logic Design: Chapter 8. Modeling Hardware using Verilog; Chapter 9. Simulation-based Verification; Chapter 10. RTL Synthesis; Chapter 11. Formal Verification, Chapter 12. Logic Optimization; Chapter 13. Technology Library; Chapter 14. Static Timing Analysis; Chapter 15. Constraints; Chapter 16. Technology Mapping; Chapter 17. Timing-driven Optimizations; Chapter 18. Power Analysis; Chapter 19. Power-driven Optimizations; Part III. Design for Testability (DFT): Chapter 20. Basics of DFT; Chapter 21. Scan Design; Chapter 22. Automatic Test Pattern Generation (ATPG); Chapter 23. Built-in Self-test (BIST); Part IV. Physical Design: Chapter 24. Basic Concepts for Physical Design; Chapter 25. Chip Planning; Chapter 26. Placement; Chapter 27. Clock Tree Synthesis (CTS); Chapter 28. Routing; Chapter 29. Physical Verification and Signoff; Chapter 30. Post-silicon Validation.
| Erscheinungsdatum | 17.07.2023 |
|---|---|
| Zusatzinfo | Worked examples or Exercises |
| Verlagsort | Cambridge |
| Sprache | englisch |
| Maße | 183 x 241 mm |
| Gewicht | 960 g |
| Themenwelt | Technik ► Elektrotechnik / Energietechnik |
| ISBN-10 | 1-009-20081-X / 100920081X |
| ISBN-13 | 978-1-009-20081-3 / 9781009200813 |
| Zustand | Neuware |
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