BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-Voltage

Chenming Hu is Distinguished Chair Professor Emeritus at UC Berkeley. He was the Chief Technology Officer of TSMC and founder of Celestry Design Technologies. He is best known for developing the revolutionary 3D transistor FinFET that powers semiconductor chips beyond 20nm. He also led the development of BSIM-- the industry standard transistor model that is used in designing most of the integrated circuits in the world. He is a member of the US Academy of Engineering, the Chinese Academy of Science, and Academia Sinica. His honors include the Asian American Engineer of the Year Award, IEEE Andrew Grove Award and Solid Circuits Award as well as Nishizawa Medal, and UC Berkeley's highest honor for teaching-- the Berkeley Distinguished Teaching Award. Harshit Agarwal received the PhD degree from Indian Institute of Technology Kanpur, India in 2017. He is currently working as center manager and post-doc fellow at Berkeley Device Modeling Centre, BSIM group, University of California Berkeley, Berkeley, USA. He has been involved in the development of multi-gate and bulk MOSFET models. He is also involved in the modeling and characterization of advanced steep sub-threshold slope devices like negative capacitance FETs, tunnel FET etc. He has authored several papers in the field of semiconductor device modeling, simulation and characterization. He is a Co-Developer of BSIM-BULK (formerly BSIM6) industry standard models for BULK-MOSFET. He has published 8 journal papers and 10 conference papers all on the development of the BSIM-BULK model. His current research interests include semiconductor device physics, modeling, and characterization. Yogesh Singh Chauhan is a Professor at the Indian Institute of Technology Kanpur. His research interests include the physics, characterization, and modeling of nanoscale semiconductor devices, and RF circuit design. He is the developer of several industry standard models, including the BSIM-BULK (BSIM6), BSIM-IMG, BSIM-CMG and ASM-HEMT models.

1. Background
2. BSIM-BULK Core Model
3. Real Device Effects
4. Leakage current and thermal effects
5. BSIM-BULK Charge and Capacitance Model
6. Noise and RF Modeling
7. Junction Diode and Layout Dependent Parasitic Model
8. Compact Modeling of High Voltage Devices
9. Parameter Extraction
10. BSIM-BULK Model Quality Testing