Mixed-Mode Simulation

1. Introduction to Mixed-Mode Simulation.- 1.1 The Simulation Problem.- 1.2 Levels of Simulation.- 1.2.1 Electrical Simulation.- 1.2.2 Gate-Level Simulation.- 1.2.3 Switch-Level Simulation.- 1.2.4 Register-Transfer Level Simulation.- 1.2.5 Behavioral Level Simulation.- 1.3 Mixed-Mode Simulation.- 1.3.1 Basic Issues in Mixed-Mode Simulation.- 1.3.2 A Survey of Existing Simulators.- 1.4 Outline of Book.- 2. Electrical Simulation Techniques.- 2.1 Equation Formulation.- 2.2 Standard Techniques for Transient Analysis.- 2.3 Time-Step Control: Theoretical Issues.- 2.3.1 Constraints on Step Size.- 2.3.2 Solution of Nonlinear Equations.- 2.4 Time-Step Control: Implementation Issues.- 2.4.1 LTE Time-Step Control.- 2.4.2 Iteration Count Time-Step Control.- 3. Relaxation-Based Simulation Techniques.- 3.1 Latency and Multirate Behavior.- 3.2 Overview of Relaxation Methods.- 3.2.1 Linear Relaxation.- 3.2.2 Nonlinear Relaxation.- 3.2.3 Waveform Relaxation.- 3.2.4 Partitioning for Relaxation Methods.- 4. Iterated Timing Analysis.- 4.1 Equation Flow for Nonlinear Relaxation.- 4.2 Timing Analysis Algorithms.- 4.3 Splice 1.7 - Fixed Time-Step ITA.- 4.4 iSplice3.1 - Global-Variable Time-Step ITA.- 4.4.1 Circuit Partitioning.- 4.4.2 Global-Variable Time-Step Control.- 4.5 Electrical Events and Event Scheduling.- 4.5.1 Latency Detection.- 4.5.2 Events and Event Scheduling.- 4.5.3 Latency in the Iteration Domain.- 5. Gate-Level Simulation.- 5.1 Introduction.- 5.2 Evolution of Logic States.- 5.2.1 Two-State Logic Model.- 5.2.2 Ternary Logic Model.- 5.2.3 A Four-State Logic Model.- 5.2.4 A Nine-State Logic Model.- 5.3 Characterization of Switching Properties.- 5.4 Logic Switching Delay Models.- 5.5 Logic Simulation Algorithm.- 6. Switch-Level Timing Simulation.- 6.1 Introduction.- 6.2 Switch-Level Simulation.- 6.3 A Generalization of the Nine-State Logic Model.- 6.4 Simulation Using the Generalized Model.- 6.4.1 Electrical-Logic Simulation.- 6.4.2 The Elogic Algorithm.- 6.4.3 Problems with the Elogic Approach.- 6.5 A Survey of Switch-Level Timing Simulators.- 6.6 The Mixed-Mode Interface.- 7. Implementation of Mixed-Mode Simulation.- 7.1 Simulator Architecture.- 7.2 Event Scheduler Design.- 7.2.1 Linear Linked-List Structure.- 7.2.2 Indexed List Methods.- 7.2.3 Classical Time-Wheel.- 7.2.4 Managing Remote Lists.- 7.2.5 Other General Scheduling Issues.- 7.3 Transient Analysis and Event Scheduling.- 7.4 DC Analysis techniques.- 7.5 Mixed-Mode Simulation Examples.- 8. Conclusions and Future Work.- 8.1 Summary.- 8.2 Areas of Future Work.- 8.2.1 Automatic Partitioning.- 8.2.2 Fault Simulation.- 8.2.3 Analog Multilevel Simulation.- 8.3 Conclusions.- References.- About the Authors.