CMOS VLSI Design

Chapter 1 Introduction

1.1 A Brief History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Preview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 MOS Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4 CMOS Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

    1.4.1 The Inverter 9

    1.4.2 The NAND Gate 9

    1.4.3 CMOS Logic Gates 9

    1.4.4The NOR Gate 11

    1.4.5 Compound Gates 11

    1.4.6 Pass Transistors and Transmission Gates 12

    1.4.7 Tristates 14

    1.4.8 Multiplexers 15

    1.4.9 Sequential Circuits 16

1.5 CMOS Fabrication and Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

    1.5.1 Inverter Cross-Section 19

    1.5.2 Fabrication Process 20

    1.5.3 Layout Design Rules 24

    1.5.4 Gate Layouts 27

    1.5.5 Stick Diagrams 28

1.6 Design Partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

    1.6.1 Design Abstractions 30

    1.6.2 Structured Design 31

    1.6.3 Behavioral, Structural, and Physical Domains 31

1.7 Example: A Simple MIPS Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . 33

    1.7.1 MIPS Architecture 33

    1.7.2 Multicycle MIPS Microarchitectures 34

1.8 Logic Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

    1.8.1 Top-Level Interfaces 38

    1.8.2 Block Diagrams 38

    1.8.3 Hierarchy 40

    1.8.4 Hardware Description Languages 40

1.9 Circuit Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

1.10 Physical Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

    1.10.1 Floorplanning 45

    1.10.2 Standard Cells 48

    1.10.3 Pitch Matching 50

    1.10.4 Slice Plans 50

    1.10.5 Arrays 51

    1.10.6 Area Estimation 51

1.11 Design Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

1.12 Fabrication, Packaging, and Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Summary and a Look Ahead 55

Exercises 57

 

Chapter 2 MOS Transistor Theory

2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2.2 Long-Channel I-V Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2.3 C-V Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

    2.3.1 Simple MOS Capacitance Models 68

    2.3.2 Detailed MOS Gate Capacitance Model 70

    2.3.3 Detailed MOS Diffusion Capacitance Model 72

2.4 Nonideal I-V Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

    2.4.1 Mobility Degradation and Velocity Saturation 75

    2.4.2 Channel Length Modulation 78

    2.4.3 Threshold Voltage Effects 79

    2.4.4 Leakage 80

    2.4.5 Temperature Dependence 85

    2.4.6 Geometry Dependence 86

    2.4.7 Summary 86

2.5 DC Transfer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

    2.5.1 Static CMOS Inverter DC Characteristics 88

    2.5.2 Beta Ratio Effects 90

    2.5.3 Noise Margin 91

    2.5.4 Pass Transistor DC Characteristics 92

2.6 Pitfalls and Fallacies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Summary 94

Exercises 95

 

Chapter 3 CMOS Processing Technology

3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

3.2 CMOS Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

    3.2.1 Wafer Formation 100

    3.2.2 Photolithography 101

    3.2.3 Well and Channel Formation 103

    3.2.4 Silicon Dioxide (SiO2) 105

    3.2.5 Isolation 106

    3.2.6 Gate Oxide 107

    3.2.7 Gate and Source/Drain Formations 108

    3.2.8 Contacts and Metallization 110

    3.2.9 Passivation 112

    3.2.10 Metrology 112

3.3 Layout Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

    3.3.1 Design Rule Background 113

    3.3.2 Scribe Line and Other Structures 116

    3.3.3 MOSIS Scalable CMOS Design Rules 117

    3.3.4 Micron Design Rules 118

3.4 CMOS Process Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

    3.4.1 Transistors 119

    3.4.2 Interconnect 122

    3.4.3 Circuit Elements 124

    3.4.4 Beyond Conventional CMOS 129

3.5 Technology-Related CAD Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

    3.5.1 Design Rule Checking (DRC) 131

    3.5.2 Circuit Extraction 132

3.6 Manufacturing Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

    3.6.1 Antenna Rules 133

    3.6.2 Layer Density Rules 134

    3.6.3 Resolution Enhancement Rules 134

    3.6.4 Metal Slotting Rules 135

    3.6.5 Yield Enhancement Guidelines 135

3.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

3.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Summary 139

Exercises 139

 

Chapter 4 Delay

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

    4.1.1 Definitions 141

    4.1.2 Timing Optimization 142

4.2 Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

4.3 RC Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

    4.3.1 Effective Resistance 146

    4.3.2 Gate and Diffusion Capacitance 147

    4.3.3 Equivalent RC Circuits 147

    4.3.4 Transient Response 148

    4.3.5 Elmore Delay 150

    4.3.6 Layout Dependence of Capacitance 153

    4.3.7 Determining Effective Resistance 154

4.4 Linear Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

    4.4.1 Logical Effort 156

    4.4.2 Parasitic Delay 156

    4.4.3 Delay in a Logic Gate 158

    4.4.4 Drive 159

    4.4.5 Extracting Logical Effort from Datasheets 159

    4.4.6 Limitations to the Linear Delay Model 160

4.5 Logical Effort of Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

    4.5.1 Delay in Multistage Logic Networks 163

    4.5.2 Choosing the Best Number of Stages 166

    4.5.3 Example 168

    4.5.4 Summary and Observations 169

    4.5.5 Limitations of Logical Effort 171

    4.5.6 Iterative Solutions for Sizing 171

4.6 Timing Analysis Delay Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

    4.6.1 Slope-Based Linear Model 173

    4.6.2 Nonlinear Delay Model 174

    4.6.3 Current Source Model 174

4.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

4.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Summary 176

Exercises 176

 

Chapter 5 Power

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

    5.1.1 Definitions 182

    5.1.2 Examples 182

    5.1.3 Sources of Power Dissipation 184

5.2 Dynamic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

    5.2.1 Activity Factor 186

    5.2.2 Capacitance 188

    5.2.3 Voltage 190

    5.2.4 Frequency 192

    5.2.5 Short-Circuit Current 193

    5.2.6 Resonant Circuits 193

5.3 Static Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

    5.3.1 Static Power Sources 194

    5.3.2 Power Gating 197

    5.3.3 Multiple Threshold Voltages and Oxide Thicknesses 199

    5.3.4 Variable Threshold Voltages 199

    5.3.5 Input Vector Control 200

5.4 Energy-Delay Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

    5.4.1 Minimum Energy 200

    5.4.2 Minimum Energy-Delay Product 203

    5.4.3 Minimum Energy Under a Delay Constraint 203

5.5 Low Power Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

    5.5.1 Microarchitecture 204

    5.5.2 Parallelism and Pipelining 204

    5.5.3 Power Management Modes 205

5.6 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

5.7 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Summary 209

Exercises 209

 

Chapter 6 Interconnect

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

    6.1.1 Wire Geometry 211

    6.1.2 Example: Intel Metal Stacks 212

6.2 Interconnect Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

    6.2.1 Resistance 214

    6.2.2 Capacitance 215

    6.2.3 Inductance 218

    6.2.4 Skin Effect 219

    6.2.5 Temperature Dependence 220

6.3 Interconnect Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

    6.3.1 Delay 220

    6.3.2 Energy 222

    6.3.3 Crosstalk 222

    6.3.4 Inductive Effects 224

    6.3.5 An Aside on Effective Resistance and Elmore Delay 227

6.4 Interconnect Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

    6.4.1 Width, Spacing, and Layer 229

    6.4.2 Repeaters 230

    6.4.3 Crosstalk Control 232

    6.4.4 Low-Swing Signaling 234

    6.4.5 Regenerators 236

6.5 Logical Effort with Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

6.6 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Summary 238

Exercises 238

 

Chapter 7 Robustness

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

7.2 Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

    7.2.1 Supply Voltage 242

    7.2.2 Temperature 242

    7.2.3 Process Variation 243

    7.2.4 Design Corners 244

7.3 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

    7.3.1 Reliability Terminology 246

    7.3.2 Oxide Wearout 247

    7.3.3 Interconnect Wearout 249

    7.3.4 Soft Errors 251

    7.3.5 Overvoltage Failure 252

    7.3.6 Latchup 253

7.4 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

    7.4.1 Transistor Scaling 255

    7.4.2 Interconnect Scaling 257

    7.4.3 International Technology Roadmap for Semiconductors 258

    7.4.4 Impacts on Design 259

7.5 Statistical Analysis of Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

    7.5.1 Properties of Random Variables 263

    7.5.2 Variation Sources 266

    7.5.3 Variation Impacts 269

7.6 Variation-Tolerant Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

    7.6.1 Adaptive Control 275

    7.6.2 Fault Tolerance 275

7.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

7.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Summary 284

Exercises 284

 

Chapter 8 Circuit Simulation

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

8.2 A SPICE Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

    8.2.1 Sources and Passive Components 288

    8.2.2 Transistor DC Analysis 292

    8.2.3 Inverter Transient Analysis 292

    8.2.4 Subcircuits and Measurement 294

    8.2.5 Optimization 296

    8.2.6 Other HSPICE Commands 298

8.3 Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

    8.3.1 Level 1 Models 299

    8.3.2 Level 2 and 3 Models 300

    8.3.3 BSIM Models 300

    8.3.4 Diffusion Capacitance Models 300

    8.3.5 Design Corners 302

8.4 Device Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

    8.4.1 I-V Characteristics 303

    8.4.2 Threshold Voltage 306

    8.4.3 Gate Capacitance 308

    8.4.4 Parasitic Capacitance 308

    8.4.5 Effective Resistance 310

    8.4.6 Comparison of Processes 311

    8.4.7 Process and Environmental Sensitivity 313

8.5 Circuit Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

    8.5.1 Path Simulations 313

    8.5.2 DC Transfer Characteristics 315

    8.5.3 Logical Effort 315

    8.5.4 Power and Energy 318

    8.5.5 Simulating Mismatches 319

    8.5.6 Monte Carlo Simulation 319

8.6 Interconnect Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

8.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Summary 324

Exercises 324

 

Chapter 9 Combinational Circuit Design

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

9.2 Circuit Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

    9.2.1 Static CMOS 329

    9.2.2 Ratioed Circuits 334

    9.2.3 Cascode Voltage Switch Logic 339

    9.2.4 Dynamic Circuits 339

    9.2.5 Pass-Transistor Circuits 349

9.3 Circuit Pitfalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

    9.3.1 Threshold Drops 355

    9.3.2 Ratio Failures 355

    9.3.3 Leakage 356

    9.3.4 Charge Sharing 356

    9.3.5 Power Supply Noise 356

    9.3.6 Hot Spots 357

    9.3.7 Minority Carrier Injection 357

    9.3.8 Back-Gate Coupling 358

    9.3.9 Diffusion Input Noise Sensitivity 358

    9.3.10 Process Sensitivity 358

    9.3.11 Example: Domino Noise Budgets 359

9.4 More Circuit Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

9.5 Silicon-On-Insulator Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

    9.5.1 Floating Body Voltage 361

    9.5.2 SOI Advantages 362

    9.5.3 SOI Disadvantages 362

    9.5.4 Implications for Circuit Styles 363

    9.5.5 Summary 364

9.6 Subthreshold Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

    9.6.1 Sizing 365

    9.6.2 Gate Selection 365

9.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

9.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Summary 369

Exercises 370

 

Chapter 10 Sequential Circuit Design

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

10.2 Sequencing Static Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

    10.2.1 Sequencing Methods 376

    10.2.2 Max-Delay Constraints 379

    10.2.3 Min-Delay Constraints 383

    10.2.4 Time Borrowing 386

    10.2.5 Clock Skew 389

10.3 Circuit Design of Latches and Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

    10.3.1 Conventional CMOS Latches 392

    10.3.2 Conventional CMOS Flip-Flops 393

    10.3.3 Pulsed Latches 395

    10.3.4 Resettable Latches and Flip-Flops 396

    10.3.5 Enabled Latches and Flip-Flops 397

    10.3.6 Incorporating Logic into Latches 398

    10.3.7 Klass Semidynamic Flip-Flop (SDFF) 399

    10.3.8 Differential Flip-Flops 399

    10.3.9 Dual Edge-Triggered Flip-Flops 400

    10.3.10 Radiation-Hardened Flip-Flops 401

    10.3.11 True Single-Phase-Clock (TSPC) Latches and Flip-Flops 402

10.4 Static Sequencing Element Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

    10.4.1 Choice of Elements 403

    10.4.2 Characterizing Sequencing Element Delays 405

    10.4.3 State Retention Registers 408

    10.4.4 Level-Converter Flip-Flops 408

    10.4.5 Design Margin and Adaptive Sequential Elements 409

    10.4.6 Two-Phase Timing Types 411

10.5 Sequencing Dynamic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

10.6 Synchronizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

    10.6.1 Metastability 412

    10.6.2 A Simple Synchronizer 415

    10.6.3 Communicating Between Asynchronous Clock Domains 416

    10.6.4 Common Synchronizer Mistakes 417

    10.6.5 Arbiters 419

    10.6.6 Degrees of Synchrony 419

10.7 Wave Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

10.8 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

10.9 Case Study: Pentium 4 and Itanium 2 Sequencing Methodologies . . . . . 423

Summary 423

Exercises 425

 

Chapter 11 Datapath Subsystems

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

11.2 Addition/Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

    11.2.1 Single-Bit Addition 430

    11.2.2 Carry-Propagate Addition 434

    11.2.3 Subtraction 458

    11.2.4 Multiple-Input Addition 458

    11.2.5 Flagged Prefix Adders 459

11.3 One/Zero Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

11.4 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

    11.4.1 Magnitude Comparator 462

    11.4.2 Equality Comparator 462

    11.4.3 K = A + B Comparator 463

11.5 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

    11.5.1 Binary Counters 464

    11.5.2 Fast Binary Counters 465

    11.5.3 Ring and Johnson Counters 466

    11.5.4 Linear-Feedback Shift Registers 466

11.6 Boolean Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

11.7 Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

    11.7.1 Parity 468

    11.7.2 Error-Correcting Codes 468

    11.7.3 Gray Codes 470

    11.7.4 XOR/XNOR Circuit Forms 471

11.8 Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

    11.8.1 Funnel Shifter 473

    11.8.2 Barrel Shifter 475

    11.8.3 Alternative Shift Functions 476

11.9 Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

    11.9.1 Unsigned Array Multiplication 478

    11.9.2 Two’s Complement Array Multiplication 479

    11.9.3 Booth Encoding 480

    11.9.4 Column Addition 485

    11.9.5 Final Addition 489

    11.9.6 Fused Multiply-Add 490

    11.9.7 Serial Multiplication 490

    11.9.8 Summary 490

11.10 Parallel-Prefix Computations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

11.11 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

Summary 494

Exercises 494

 

Chapter 12 Array Subsystems

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

12.2 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

    12.2.1 SRAM Cells 499

    12.2.2 Row Circuitry 506

    12.2.3 Column Circuitry 510

    12.2.4 Multi-Ported SRAM and Register Files 514

    12.2.5 Large SRAMs 515

    12.2.6 Low-Power SRAMs 517

    12.2.7 Area, Delay, and Power of RAMs and Register Files 520

12.3 DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

    12.3.1 Subarray Architectures 523

    12.3.2 Column Circuitry 525

    12.3.3 Embedded DRAM 526

12.4 Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

    12.4.1 Programmable ROMs 529

    12.4.2 NAND ROMs 530

    12.4.3 Flash 531

12.5 Serial Access Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

    12.5.1 Shift Registers 533

    12.5.2 Queues (FIFO, LIFO) 533

12.6 Content-Addressable Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

12.7 Programmable Logic Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

12.8 Robust Memory Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

    12.8.1 Redundancy 541

    12.8.2 Error Correcting Codes (ECC) 543

    12.8.3 Radiation Hardening 543

12.9 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544

Summary 545

Exercises 546

 

Chapter 13 Special-Purpose Subsystems

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

13.2 Packaging and Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

    13.2.1 Package Options 549

    13.2.2 Chip-to-Package Connections 551

    13.2.3 Package Parasitics 552

    13.2.4 Heat Dissipation 552

    13.2.5 Temperature Sensors 553

13.3 Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

    13.3.1 On-Chip Power Distribution Network 556

    13.3.2 IR Drops 557

    13.3.3 L di/dt Noise 558

    13.3.4 On-Chip Bypass Capacitance 559

    13.3.5 Power Network Modeling 560

    13.3.6 Power Supply Filtering 564

    13.3.7 Charge Pumps 564

    13.3.8 Substrate Noise 565

    13.3.9 Energy Scavenging 565

13.4 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

    13.4.1 Definitions 566

    13.4.2 Clock System Architecture 568

    13.4.3 Global Clock Generation 569

    13.4.4 Global Clock Distribution 571

    13.4.5 Local Clock Gaters 575

    13.4.6 Clock Skew Budgets 577

    13.4.7 Adaptive Deskewing 579

13.5 PLLs and DLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580

    13.5.1 PLLs 580

    13.5.2 DLLs 587

    13.5.3 Pitfalls 589

13.6 I/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590

    13.6.1 Basic I/O Pad Circuits 591

    13.6.2 Electrostatic Discharge Protection 593

    13.6.3 Example: MOSIS I/O Pads 594

    13.6.4 Mixed-Voltage I/O 596

13.7 High-Speed Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

    13.7.1 High-Speed I/O Channels 597

    13.7.2 Channel Noise and Interference 600

    13.7.3 High-Speed Transmitters and Receivers 601

    13.7.4 Synchronous Data Transmission 606

    13.7.5 Clock Recovery in Source-Synchronous Systems 606

    13.7.6 Clock Recovery in Mesochronous Systems 608

    13.7.7 Clock Recovery in Pleisochronous Systems 610

13.8 Random Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

    13.8.1 True Random Number Generators 610

    13.8.2 Chip Identification 611

    13.9 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

Summary 613

Exercises 614

 

Chapter 14 Design Methodology and Tools

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

14.2 Structured Design Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

    14.2.1 A Software Radio—A System Example 618

    14.2.2 Hierarchy 620

    14.2.3 Regularity 623

    14.2.4 Modularity 625

    14.2.5 Locality 626

    14.2.6 Summary 627

14.3 Design Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

    14.3.1 Microprocessor/DSP 627

    14.3.2 Programmable Logic 628

    14.3.3 Gate Array and Sea of Gates Design 631

    14.3.4 Cell-Based Design 632

    14.3.5 Full Custom Design 634

    14.3.6 Platform-Based Design—System on a Chip 635

    14.3.7 Summary 636

14.4 Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

    14.4.1 Behavioral Synthesis Design Flow (ASIC Design Flow) 637

    14.4.2 Automated Layout Generation 641

    14.4.3 Mixed-Signal or Custom-Design Flow 645

14.5 Design Economics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

    14.5.1 Non-Recurring Engineering Costs (NREs) 647

    14.5.2 Recurring Costs 649

    14.5.3 Fixed Costs 650

    14.5.4 Schedule 651

    14.5.5 Personpower 653

    14.5.6 Project Management 653

    14.5.7 Design Reuse 654

14.6 Data Sheets and Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

    14.6.1 The Summary 655

    14.6.2 Pinout 655

    14.6.3 Description of Operation 655

    14.6.4 DC Specifications 655

    14.6.5 AC Specifications 656

    14.6.6 Package Diagram 656

    14.6.7 Principles of Operation Manual 656

    14.6.8 User Manual 656

14.7 CMOS Physical Design Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

14.8 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

Exercises 657

 

Chapter 15 Testing, Debugging, and Verification

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

    15.1.1 Logic Verification 660

    15.1.2 Debugging 662

    15.1.3 Manufacturing Tests 664

15.2 Testers, Test Fixtures, and Test Programs . . . . . . . . . . . . . . . . . . . . . . . . . . 666

    15.2.1 Testers and Test Fixtures 666

    15.2.2 Test Programs 668

    15.2.3 Handlers 669

15.3 Logic Verification Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

    15.3.1 Test Vectors 670

    15.3.2 Testbenches and Harnesses 671

    15.3.3 Regression Testing 671

    15.3.4 Version Control 672

    15.3.5 Bug Tracking 673

15.4 Silicon Debug Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

15.5 Manufacturing Test Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

    15.5.1 Fault Models 677

    15.5.2 Observability 679

    15.5.3 Controllability 679

    15.5.4 Repeatability 679

    15.5.5 Survivability 679

    15.5.6 Fault Coverage 680

    15.5.7 Automatic Test Pattern Generation (ATPG) 680

    15.5.8 Delay Fault Testing 680

15.6 Design for Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681

    15.6.1 Ad Hoc Testing 681

    15.6.2 Scan Design 682

    15.6.3 Built-In Self-Test (BIST) 684

    15.6.4 IDDQ Testing 687

    15.6.5 Design for Manufacturability 687

15.7 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688

15.8 Testing in a University Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

15.9 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

Summary 697

Exercises 697

 

Appendix A Hardware Description Languages

A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

    A.1.1 Modules 700

    A.1.2 Simulation and Synthesis 701

A.2 Combinational Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

    A.2.1 Bitwise Operators 702

    A.2.2 Comments and White Space 703

    A.2.3 Reduction Operators 703

    A.2.4 Conditional Assignment 704

    A.2.5 Internal Variables 706

    A.2.6 Precedence and Other Operators 708

    A.2.7 Numbers 708

    A.2.8 Zs and Xs 709

    A.2.9 Bit Swizzling 711

    A.2.10 Delays 712

A.3 Structural Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

A.4 Sequential Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

    A.4.1 Registers 717

    A.4.2 Resettable Registers 718

    A.4.3 Enabled Registers 719

    A.4.4 Multiple Registers 720

    A.4.5 Latches 721

    A.4.6 Counters 722

    A.4.7 Shift Registers 724

A.5 Combinational Logic with Always / Process Statements . . . . . . . . . . . . . . 724

    A.5.1 Case Statements 726

    A.5.2 If Statements 729

    A.5.3 SystemVerilog Casez 731

    A.5.4 Blocking and Nonblocking Assignments 731

A.6 Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

    A.6.1 FSM Example 735

    A.6.2 State Enumeration 736

    A.6.3 FSM with Inputs 738

A.7 Type Idiosyncracies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740

A.8 Parameterized Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

A.9 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

    A.9.1 RAM 745

    A.9.2 Multiported Register Files 747

    A.9.3 ROM 748

A.10 Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

A.11 SystemVerilog Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754

A.12 Example: MIPS Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

    A.12.1 Testbench 756

    A.12.2 SystemVerilog 757

    A.12.3 VHDL 766

Exercises 776

References 785

Index 817

Credits 838