A Hardware Track-Trigger for CMS (eBook)

Supervisor’s Foreword 7
Abstract 9
Acknowledgements 10
Contents 11
Acronyms 14
1 Introduction 17
1.1 Theory and Motivation 17
1.2 The Large Hadron Collider 18
1.3 The Compact Muon Solenoid 18
1.3.1 Tracker 19
1.3.2 Electromagnetic Calorimeter 19
1.3.3 Hadronic Calorimeter 21
1.3.4 Muon Detectors 21
1.3.5 Trigger and Data Acquisition 22
1.4 Field Programmable Gate Arrays 23
References 24
2 The CMS Phase II Upgrade 26
2.1 The High-Luminosity LHC 26
2.2 Motivation for an Upgraded CMS Tracker 26
2.3 The Phase II Outer Tracker Design and Geometry 27
2.4 The pT-Modules 29
2.4.1 Front-End Electronics 31
2.4.2 Sensor Type 32
2.5 Module Prototyping and Beam Tests 33
2.5.1 Test Beam Apparatus 33
2.5.2 Test Beam Results 34
2.6 Back-End Electronics 36
References 39
3 The Track Finder Demonstrator 41
3.1 L1 Tracking Requirements 41
3.2 Proposed Track Finder System Architecture 42
3.2.1 A Time-Multiplexed Trigger 42
3.2.2 Data Delivery and Regional Segmentation 43
3.3 The Track Finder Demonstrator 44
3.3.1 Overview of Firmware Architecture 44
3.3.2 The Demonstrator Hardware 46
References 51
4 The Hough Transform 53
4.1 The Hough Transform Algorithm 53
4.2 Firmware Implementations 57
4.2.1 Systolic Array Implementation 57
4.2.2 Pipelined Implementation 61
4.2.3 Daisy Chain Implementation 63
4.3 Hough Transform Preprocessor 68
4.3.1 HTP Mathematics Block 69
4.4 Hough Transform Results 73
4.4.1 Optimisations and Improvements 78
4.5 Scaling to Ultrascale and Ultrascale+ FPGAs 80
References 82
5 The Kalman Filter 83
5.1 The Kalman Filter Algorithm 83
5.1.1 The Generic Kalman Filter 83
5.1.2 The Kalman Track Fitter 85
5.1.3 The Kalman State Updater 89
5.1.4 The Kalman Filter Flow Control 90
5.2 Resource Usage and Latency 93
5.3 Potential for Improvements 94
5.4 Seed Filter and Linear Regression Fit 96
5.5 Duplicate Removal 97
5.5.1 Algorithm 97
5.5.2 Implementation 98
References 100
6 Demonstrator Results 102
6.1 Demonstrator Configuration and Data Format 102
6.2 Tracking Efficiency and Purity 104
6.3 Track Parameter Resolution 107
6.4 Data Rates and Limitations 112
6.5 Tracking Robustness 115
6.6 Track Finding Down to 2GeV 116
6.7 Latency Measurements 118
6.8 The Evolution of the Track Finder 119
6.8.1 Rejected Ideas 121
6.9 FPGA Resource Usage 122
6.10 The Associative Memory Track Finder 123
6.11 The Tracklet Track Finder 125
References 126
7 Outlook and Summary 127
7.1 Demonstrator Scaling 127
7.2 Projected Final System Technology 130
7.2.1 Outer Tracker Data, Trigger and Control Board 130
7.2.2 Track Finding Processor Board 130
7.3 Summary 132
References 132