High-Level Test Synthesis of Digital VLSI Circuits

Explains how HTS is able to explore the synthesis freedom provided at high-level to derive an inherently testable architecture at low or even overhead. This text provides an introduction to HTS and helps develop an understanding of this emerging technology.

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Explaining how HTS is able to explore the synthesis freedom provided at high-level to derive an inherently testable architecture at low or even no overhead, this text provides an introduction to HTS and helps develop an understanding of this emerging technology by presenting a background of HTS terms, operation scheduling and resource allocation algorithms. The book also covers various HTS techniques for scan and built-in self-test methodologies, register-transfer level test synthesis, examples of several effective HTS schemes for highly testable digital circuits, and more.