A Guide to VHDL

Intended for the engineer who needs to develop, document, simulate and synthesize a design using the VHDL language, this is a guide for system and chip designers who are working with VHDL CAD tools and who have some experience programming in FORTRAN, PASCAL or C and have used a logic simulator.

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"A Guide to VHDL" is intended for the working engineer who needs to develop, document, simulate and synthesize a design using the VHDL language. It is a guide for system and chip designers who are working with VHDL CAD tools and who have some experience programming in FORTRAN, PASCAL or C and have used a logic simulator. The work includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises included in the chapter can be run to reinforce the learning experience. For practical purposes, the book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases. The guide can be used as a primer since its contents are appropriate for an introductory course in VHDL.