Learning from VLSI Design Experience (eBook)

Weng Fook Lee is a distinguished Technical Director at Emerald Systems Design Center with 25 years of IC Design experience. Lee has vast experience in designing with Verilog and VHDL, and is an internationally acknowledged expert in the field of RTL coding and logic synthesis for ASIC/FPGA/SOC. Lee is an expert in synthesizing and tweaking synthesis for performance and low power, leading enhanced methodology to address advanced DFT techniques for VDSM technology, development and deployment of low power standard cell libraries. Lee have lead the development of new architectures and micro-architectures for efficient PMSM motion control ASIC and have developed architectures for AI classification algorithms implementation in ASIC. Lee published “VHDL Coding and Logic Synthesis with Synopsys" with Academic Press Publication, US (ISBN: 0-12-440651-3) in May 2000, "Verilog Coding for Logic Synthesis" with John Wiley Publication, US (ISBN: 0-471-42976-7) in April 2003, “VLIW Microprocessor Hardware Design for ASICs and FPGA” with McGraw Hill Publication, US (ISBN: 978-0071497022) in Aug 2007. Lee is also the inventor and co-inventor of 14 design patents granted by the US Patent and Trademark Office. 

Dedication 5
Preface 6
Trademarks 9
Acknowledgment 10
Contents 11
List of Figures 14
List of Tables 20
List of Examples 21
Chapter 1: Introduction 24
Chapter 2: Design Methodology and Flow 25
Analog/Custom Design Flow 25
Digital Design Flow (Fig. 2.7) 29
Synthesis 51
Standard Cell Library 51
Design Constraints 53
Input Delay 54
Output Delay 54
Path Delay 55
Clock Specification 55
Multicycle Path 56
False Path 57
Synthesis Optimizations to Improve Timing 57
Importance of Clock in Backend 60
Floor Plan 61
Clock Tree Synthesis 65
Chapter 3: Multiple Clock Design 67
Mean Time Between Failure 68
Synchronizer 71
Receiving Clock Faster than Transmitting Clock 71
Transmitting Clock Faster than Receiving Clock 74
Reset 84
Chapter 4: Latch Inference 88
If-Else Statement 89
Case Statement 91
Chapter 5: Design for Test 93
Scan Chain 94
Before Scan 94
After Scan 97
Automatic Test Pattern Generation (ATPG) 98
Test Compression 99
Scan Chain Crossing Different Clock Domains During Shift Phase of ATPG 102
Scan Chain for Design with Different Power Domains 109
Capture Phase of ATPG for Multiple Clock Design 111
Logic Built in Self-Test 113
How Does Logic BIST Work 113
Implementation of Logic BIST 114
Memory BIST 123
Chapter 6: Signed Verilog 130
Mixing Signed and Unsigned 130
Multiplication and Division of Signed and Unsigned Values 136
Unsigned Shifting in Verilog 138
Signed Shifting in Verilog 141
Rounding Down Due to Signed Shift Right 144
Simulating RTL Using Signed and Unsigned 146
Chapter 7: State Machine 149
RTL Verilog for a State Machine 149
RTL Coding Style for State Machine Using Two Always Processes 156
Different RTL Coding Styles for State Machine 156
When to Use One-Hot, Gray, or Binary Encoding 166
Blocking Statements 167
Non-blocking Statements 170
Rule of Thumb when Using Non-blocking Statement and Blocking Statement 173
Chapter 8: RTL Coding Guideline 176
Contention 176
Sensitivity List 178
Level-Sensitive and Edge-Sensitive RTL 181
Edge-Sensitive RTL Verilog Code 181
Level-Sensitive RTL Verilog Code 184
Mixing Level-Sensitive and Edge-Sensitive Verilog Code 185
Input, Output, and Bidirectional Ports in RTL 186
Blocking and Non-blocking Statement 186
Inferred Latch 187
Signed and Unsigned 187
Logic between Blocks 187
Register Output of Blocks 188
Naming Convention 190
Chapter 9: Code Coverage 192
Flow for Code Coverage 192
Types of Code Coverage 193
Simulation with Code Coverage 194
Enhancing Testbench to Increase Code Coverage 212
References 227
Index 228