Gallium Arsenide Digital Circuits

1: Introduction.- 1.1 Gallium Arsenide.- 1.2 Electronic properties of GaAs.- 1.3 Velocity-field relation.- 1.4 GaAs transistor structures, MESFET, HFET, HBT.- 1.5 Scope.- References.- 2: Circuit Models of the MESFET.- 2.1 Introduction.- 2.2 Schottky junction.- 2.3 Drain current.- 2.4 Gate current.- 2.5 Capacitive currents.- 2.6 Charge-based model for circuit simulation.- 2.7 Capacitance-based model.- 2.8 Parasitic elements.- 2.9 Small signal model.- 2.10 Empirical model.- 2.11 Summary.- References.- 3: Enhancement-Depletion Logic Circuits.- 3.1 Introduction.- 3.2 Simplified device model for circuit design.- 3.3 E-D logic.- 3.4 Noise margin analysis.- 3.5 Pull-up delay.- 3.6 Pull-down delay.- 3.7 Fan-out and fan-in.- 3.8 NOR, NAND.- 3.9 Flip flops.- 3.10 Remarks.- References.- 4: Transmission-Gate Logic.- 4.1 Introduction.- 4.2 Analysis.- 4.3 Allowable range of VG.- 4.4 Shift register.- 4.5 Cross point switch.- 5: Buffered ED Logic Circuits.- 5.1 Source follower.- 5.2 EDSF logic.- 5.3 EDSFD logic.- 5.4 EDSB logic.- 5.5 SPED logic.- 5.6 Split-phase super buffer.- 5.7 Ring oscillator.- 5.8 Summary.- References.- 6: Source-Coupled Logic Circuits.- 6.1 Source-coupled differential pair.- 6.2 Observations.- 6.3 Noise margins and delays.- 6.4 Threshold variation.- 6.5 Source-coupled logic.- 6.6 Cascode differential pair.- 6.7 Summary.- Reference.- 7: Subsystems Design.- 7.1 Introduction.- 7.2 Lightwave communications system.- 7.3 Pulse width preservation.- 7.4 Time-multiplexer/demultiplexer.- 7.5 Cross-point switch.- 7.6 Time- and Time-space-switches.- 7.7 Static random access memory.- 7.8 O/E-E/O repeater.- 7.9 Remarks.- References.