Implementation issues of flexible high-throughput turbo-code decoders for high code rates

Abstract
The evolution of wireless communication systems has benefited both from advances in
information theory and semiconductor technology. As a result, wirelessly connected handheld
devices are ubiquitous in our information centric society which requires ever higher
data rates at ever lower latencies. This is reflected in the evolution of the 3GPP mobile
communication standards. Data rates in the order of tens of Gb/s, roundtrip latencies of
less than 1 ms and code rates close to 1 are going to be used in the upcoming 5G standards.
Thus, the main requiremets for the baseband signal processing of todays and future wireless
communication systems are: High data rates, high code rates and low processing latencies.
The channel decoder, which is used for forward error correction (FEC) in wireless baseband
signal processing is a major source of computational complexity and power consumption.
For the 3GPP standards, Turbo-Codes have been adopted as the channel code for the
downlink shared channel. Turbo-Codes offer excellent error correcting performance and
flexibility with respect to code rates and code block sizes.
In this thesis, I cover my contributions to the well established research on Turbo-Code
decoding. I present new algorithmic and architectural solutions to enable significant improvements
for current and upcoming mobile communication systems. The respective implementation
issues for flexible high throughput decoders for high code rates are investigated.
For the pipelined XMAP Turbo-Code decoder architecture, I evaluate the impact of
a bit-level pipelining technique as well as impact of the trellis compression technique on
throughput, latency and decoder area for fully LTE compatible case study hardware implementations.
On algorithmic level, I present advanced iteration control techniques on
transport block and code block level, which employ the CRC based error detection of LTE
to decrease the decoding latency. Furthermore, I present techniques for significantly improving
the error correcting performance of state-of-the-art PMAP Turbo-Code decoder
architectures for high code rates close to 1 and small code block sizes < 248 bit. These
techniques are then combined in a cross-layer approach and demonstrated in a fully LTE-A
Pro compatible Turbo-Code decoder hardware architecture.