Integration of SRAM-FPGAs for Hardware Acceleration of a Data Processing Module for Space Instruments

Space probes and satellites for scientific space missions consist of a spacecraft platform that carries several scientific instruments such as telescopes and spectrometers. Complex instruments like the PHI instrument on Solar Orbiter (SoPHI) feature a dedicated Data Processing Unit (DPU). Sensor resolution and acquisition speed for those space instruments increase rapidly, but the data rate to downlink this data increases only slowly as it requires costly ground stations. Compression alone does not provide enough data reduction in cases such as the SoPHI instrument. In Solar Orbiter, on-board processing from acquired image data to a map of magnetic field parameters is required. The processors currently available for space applications do not have sufficient processing power. Field Programmable Gate Arrays (FPGA) based on SRAM configuration memory are available for space applications and the data processing required for Solar Orbiter has been demonstrated on them. This thesis presents two DPU architectures that combine a processor for general control of the instrument with an attached FPGA for accelerated data processing. For the two architectures a data bridge to connect to the FPGA is presented, as well as configuration controllers managed by software running on the processor. The first DPU architecture consists of two FPGAs: one antifuse FPGA to house the processor, interface, and configuration controller and two SRAM FPGAs to offload processing. The second DPU architecture adds a more powerful ASIC processor to the antifuse and SRAM FPGAs. The integration of the bridge and processor in one FPGA allows to use direct memory access from the interface, but limits the speed of the processor that can be used. While the bridges for both architectures differ significantly, they both attach to a Network-on-Chip with path addressing. As there is only one controlling processor in this Network-on-Chip the thesis contributes a protocol simple enough to implement a handler in each hardware node. The distinct aspect in designing a computer for space applications is to deal with the harsh environment, specifically with ionizing particle radiation. Based on a discussion of effects of this radiation on CMOS logic and radiation environment, this thesis estimates upset rates in the FPGAs. Furthermore, fault injection was performed on the design to quantify the number of upsets that result in erroneous behavior and to classify faults.