Highly Area- and Energy-Efficient QR-Decomposition CMOS Macros for a Wide Range of Applications

Abstract

Number crunching matrix decomposition accelerators are attractive SoC components formany applications with a wide range of specifications. In this thesis, a new family of highlyarea- and energy-efficient, modular matrix decomposition architectures based on the Givensalgorithmand CORDIC- (Coordinate Rotate Digital Computer) rotations are elaborated. Theresulting parameterized architecture template allows for implementations of real-/complex-valuedand integer/floating-point QRD co-processors and matches a wide range of application requirements.In order to achieve high area- and energy-efficiency a systematic design space explorationhas to be applied. Based on the architecture template and pre-characterization of basicbuilding blocks an accurate algebraic cost-model, enabling for early cost estimation is presented.It allows for cross-layer design space exploration over architecture, micro-architectureand circuit-level using a rich set of parameters with adequate accuracy in reasonable time. Thenumerical accuracy of the underlying CORDIC structure is thorougly investigated by bit-truesimulations and based on the results the numerical stability of the whole QRD is analysed by ahybrid analytical / simulative approach. Quantitative results for different QRD applications arepresented for implementation in 40-nm CMOS technology and proving the significant improvementof efficiency. As an exemplary result, a 16