In Search of the Next Memory (eBook)

Roberto Gastaldi was born in Reggio Emilia, Italy in 1953. He received the laurea degree in Electronic Engineering from Politecnico of Milano in 1977. He attended a postgraduate course in solid-state physics at Perugia University in 1978 and a postgraduate course in Business management at Bocconi University (Milano) in 1995. In 1977 he joined SGS-ATES (later STMicrolectronics) in Agrate Brianza (Milano) where he was involved as a device engineer in central R&D department. In 1980 he moved to memory design team working on first EPROM and EEPROM products development and later as a responsible of EPROM design team he was in charge of the EPROM family design scaling roadmap. He was involved in early 256K to 8Mb Flash-NOR product development and as a member of technical staff he contributed to industrialization of first Flash-NOR products In 2000 he took the lead of RAM design team to design SRAM and PSRAM to be used in MCP products creating from scratch a 512K-16Mb SRAM and 32-64-128Mb PSRAM product family In 2003 he started to work on PCRAM technology development and in 2006 was co-owner of the first 128Mb PCM product worldwide in 90nm technology. In 2008 he joined Micron Semiconductor and was responsible for Emerging Memory design team, since then he made evaluations and feasibility studies on different emerging memory technologies such as T-RAM, Fe-RAM, STT-RAM. His present interests are on smart Error Correction architectures and 3D memory systems. Mr. Gastaldi owns more than 50 US granted patents and a number of publications concerning NVM design. He served as a member of ISSCC International technical Memory subcommittee from 2009 to 2011 and he chaired ISSCC2010 non-volatile memory session in 2010. He was a member of the winner team of “innovator of the year” award for EDN in 2009. Mr. Gastaldi has been a lecturer on selected topics on Microelectronics at Pavia University in 2008-2014 and since 2014 he is a member of Catrene Application steering group. Mr. Gastaldi is a member of IEEE Giovanni Campardo was born in Bergamo, Italy, in 1958. He received the laurea degree in Nuclear Engineering from the Politecnico of Milan in 1984. In 1997 he graduated in physics from the Universita’ Statale di Milano, Milan. After a short experience in the field of laser in 1984, he joined in the VLSI division of SGS (now STMicroelectronics) Milan, where, as a Project Leader, he designed the family of EPROM nMOS devices (512k, 256k, 128k and 64k) and a Look-up-table-based EPROM FIR in CMOS technology. From 1988 to 1992, after resigning from STMicroelectronics, he worked as an ASIC designer, realizing four devices. In 1992 he joined STMicroelectronics again, concentrating on Flash memory design for the microcontroller division, as a Project leader. Here he has realized a Flash + SRAM memory device for automotive applications and two embedded Flash memories (256k and 1M) for ST10 microcontroller family. Since 1994 he has been responsible for Flash memory design inside the Memory Division of SGS-Thomson Microelectronics where he has realized two double-supply Flash Memories (2M and 4M) and the single supply 8M at 1.8V. He was the Design Manager for the 64M multilevel Flash project. Up to the end of 2001 he was the Product Development Manager for the Mass Storage Flash Devices in STMicroelectronics Flash Division realizing the 128M multilevel Flash and a test pattern to store more than 2bit/cell. From 2002 to 2007, inside the ST Wireless Flash Division, he had the responsibility of building-up a team to develop 3D Integration in the direction of System-in-Package solutions. From 2007 to 2010 he was the Director of the Card Business Unit inside the Numonyx DATA NAND Flash Group. In 2010 Micron acquired Numonyx and, after a short time in Micron he moved in a company, as Design Director, for the EWS testing board design. In 2013 he joint Micron again as MANAGED MEMORY SYSTEMS MANAGER. From September 2014 he is in STM, in the Automotive Product Group, in the R&D design group. He is author/co-author of more than 100 patents and some publications and author/co-author of the books: "Flash Memories", Kluwer Academic Publishers, 1999, and the book “Floating Gate Devices: Operation and Compact Modeling”, Kluwer Academic Publishers, January 2004. Author of the book “Design of Non Volatile Memory”, Franco Angeli, 2000, and “VLSI-Design of Non-Volatile Memories”, Springer Series in ADVANCED MICROELECTRONICS, 2005.  “Memorie in Sistemi Wireless”, Franco Angeli Editore, collana scientifica, serie di Informatica, 2005. “Memories in Wireless Systems”, in CIRCUITS AND SYSTEMS, Springer Verlag, 2008. G. Campardo, F. Tiziani, M. Iaculo “Memory Mass Storage”, Springer Verlag, March 2011. He was the Co-Chairs for the “System-In-Package-Technologies” Panel discussion for the IEEE 2003 Non-Volatile Semiconductor Memory Workshop, 19th IEEE NVSMW, Monterey; Ca.  Mr. Campardo was the co-Guest Editor for the Proceeding of the IEEE, April 2003, Special issue on Flash Memory and the co-Guest Editor for the Proceeding of the IEEE, Special issue on 3D Integration Technology, January 2009. He was lecturer in the “Electronic Lab” course at the University Statale of Milan from ’96 to ’98.  In 2003, 2004 and 2005 he was the recipient for the “ST Exceptional Patent Award".

Preface 5
Contents 8
Editors and Contributors 9
1 Introduction 17
References 21
2 Historical Overview of Solid-State Non-Volatile Memories 22
1 The Story 22
References 40
3 Physics and Technology of Emerging Non-Volatile Memories 41
1 Challenges in Floating-Gate Memory Scaling 41
2 The Future of the Floating-Gate Concept 45
2.1 System-Level Management Techniques 45
2.2 Dielectric-Materials Engineering 46
2.3 Novel Flash Architectures 47
3 Alternative Storage Concepts 49
3.1 Ferroelectric Memories 50
3.2 Magneto-Resistive Memories 52
3.3 Phase-Change Memories 53
3.4 Resistive RAM 55
4 Scaling Path and Issues in Various Emerging Architectures 57
References 58
4 Performance Demands for Future NVM 61
1 Introduction 61
2 Evolution of NAND 62
3 Exploiting the 3rd Dimension: 3D NAND 66
4 Breakthrough Approach: Emerging Memories 69
4.1 Phase Change Memories (PCM) 72
4.2 Resistive RAMs (ReRAM) 79
4.3 The Challenge of Dram Replacement: STT-RAM and FeRAM 84
4.4 Ferroelectric Memories (FeRAM) 92
4.5 Final Considerations 97
References 100
5 Array Organization in Emerging Memories 102
1 Introduction 102
2 PCM and Array Organization for Unipolar Operation 103
3 Bipolar-Operation Array Organization 114
4 Ferroelectric Memory Architecture 117
5 Cross-Point Array 120
6 Write Circuits 126
6.1 Introduction 126
6.2 Writing PCM Memories 126
6.3 Writing ReRAM (Bipolar) and STT-MRAM 131
7 Redundancy 136
7.1 Introduction 136
7.2 Redundancy Schematic 137
References 140
6 Data Sensing in Emerging NVMs 141
1 Introduction 141
2 Sensing Concept in Flash and DRAM Memory 142
3 The Concept of Read Window 145
3.1 Sensing Resistance Variations in Memory Cells 148
4 Sensing in STT-MRAM 153
5 Sensing in Ferroelectric Memories 157
References 162
7 Algorithms to Survive: Programming Operation in Non-Volatile Memories 164
1 Why Algorithms to Write and Erase Non-volatile Memories? 164
2 Introduction to Flash Algorithms 166
3 Write Algorithms for PCMs 169
3.1 Introduction 169
3.2 Bi-level Programming 171
3.3 Multi-level Programming 175
4 Phase Distribution in ML Programming 179
4.1 Drift Dependence on Programmed Resistance 182
4.2 Temperature Dependence on Programmed Resistance 183
5 Write Algorithms for ReRAMs 184
5.1 ReRAM Technology Overview 185
5.2 ReRAM Cell Configuration 186
5.3 The Stochastic Variability Problem in ReRAM 187
5.4 ReRAM Program Algorithm, an ISPP Implementation 188
Acknowledgements 190
References 191
8 Error Management 195
1 The Role of ECC for Mainstream and Emerging Memory 195
2 Basics of Error Correcting Codes 197
2.1 Linear Block Codes—Basic Facts 197
2.2 Linear Block Codes Matrix Description 199
2.3 Error Correction Performance of Linear Block Codes 199
2.4 Code Modifications 202
2.5 Technology-Independent Estimates 202
3 Interesting Codes 203
3.1 Single-Parity-Check Codes 203
3.1.1 Definition 203
3.1.2 Implementation 204
3.2 Hamming Codes 204
3.2.1 Definition 205
3.2.2 Decoding 206
3.2.3 Fully Parallel Implementation 207
3.3 BCH Codes 209
3.3.1 Primer on Finite Fields 210
3.3.2 Definition 212
3.3.3 Decoding 215
3.3.4 Implementation of BM Decoding 218
4 Ultra-Fast Double Error Correcting BCH Codes 220
4.1 Elementary Operations in {/hbox{GF}}/left( {2^{m} } /right) 221
4.1.1 Multiplication by a Constant 222
4.1.2 Multiplication of Two Variables 223
4.1.3 Powers 223
4.2 Syndrome Evaluation 225
4.3 Error-Locator-Polynomial Analysis 226
4.4 Decoder Architecture 227
4.4.1 Syndrome Evaluation 228
4.4.2 Error Locator Polynomial 228
4.4.3 Root Search 230
4.4.4 Estimates 230
5 Example of Implementation on PCM Devices 231
5.1 Effective Consumption, Time and Area Overhead 232
6 Conclusions 234
Acknowledgements 235
Appendix 235
References 236
9 Emerging Memories in Radiation-Hard Design 239
1 Introduction 239
2 Radiation Environments 240
3 Effects of Radiation on Semiconductors 240
4 Radiation Effects in Memories 246
5 Radiation Immunity of Emerging Memories 248
6 Design of Radiation-Hardened Memories 250
7 Conclusions 255
Acknowledgements 255
References 255
Index 257