Architectural exploration of carrier synchronization for TDMA based satellite communication systems

Abstract
The transmission of data over a wireless channel results in frequency and phase offsets.
These offsets are generated due to unknown transmission delays between transmitter and
receiver, oscillator instabilities, and the Doppler Effect. Estimation of frequency and phase
offset, and correction of the received signal accordingly is called carrier synchronization. As
the advancement of digital modulation and coding schemes continues, the task of carrier
synchronization becomes more and more challenging since the new standards require highthroughput
functionality at low signal-to-noise-ratio (SNR). In order to fulfill these
requirements, it is vital to design efficient hardware and low complexity algorithms for carrier
synchronization. This thesis explores architectures and algorithms of carrier synchronization
which are best suited for high throughput TDMA burst-mode satellite communication
systems.
Carrier synchronization algorithms can be classified into three categories: (1) Data-
Aided (DA), (2) Non Data-Aided (NDA), and (3) Code-Aided (CA). The former shows
excellent communication performance if the burst contains ample number of known symbols
(preamble, pilot, postamble). Similarly, the NDA synchronization algorithm exhibits good
quality synchronization if the burst is transmitted at moderate or high SNR. This thesis
thoroughly investigates communication performance of various NDA and DA algorithms.
Their advantages and disadvantages are compared and the improved schemes are proposed.
The proposed schemes make use of the advantages of state-of-the-art algorithms and
compensate their drawbacks, and obtain better performance. To implement the proposed
NDA/DA carrier synchronization algorithms, we present a high-throughput and low-latency
architecture while offering the flexibility on multiple modulation schemes and burst
structures. The resulting area-efficient design easily fits into a low-end FPGA. The proposed
NDA/DA carrier synchronization algorithms employ Fast Fourier Transform (FFT) which is
very complex from implementation point of view. To reduce the implementation complexity
of traditional FFT, we explore pruned FFT algorithms and propose a corresponding novel
architectures.
In Turbo-Code decoder based modern wireless communication receivers, the quality of
NDA/DA carrier synchronization can be further improved by integrating the synchronization
step into the iterations of Turbo-Code decoder. This principle is called CA synchronization.
The integration of CA synchronization into the iterations of channel decoder is a very
challenging task because it may adversely affect the throughput and latency of Turbo-Code
decoder. Besides presenting a low complexity CA synchronization algorithm, we also propose
the corresponding architecture which is computationally efficient and achieves a very high
throughput. The resulting design can run in parallel with the Turbo-Code decoder and
therefore does not degrade the hardware performance of Turbo-Code decoder. Last but not
least, we present a high throughput architecture for constellation demapper.