Hardware Security and Trust (eBook)

Nicolas Sklavos is an Associate Professor, with the Computer Engineering & Informatics Department, Polytechnic School, University of Patras, Hellas. He holds an award for his PhD thesis on “VLSI Designs of Wireless Communications Security Systems”, from IFIP VLSI SOC, Germany, 2003. He has been awarded with a post-doctoral research scholarship, from the National Scholarship Foundation. He has participated in a great number of European and National projects, with both research & management activities, funding by the European Commission or/and National resources. He also acts as a reviewer and evaluator for both European Commission Project Calls, and National Project Calls of several countries. He is Associate Editor of the Electrical & Computer Engineering Journal, Hindawi and Cryptography, ΜDPI Publisher. He was the Editor in Chief of Information Security Journal: a Global Perspective, Taylor Francis Group, from 2011 to 2014. He also served as Associate Editor of IEEE Transactions of Latin America, and Computers & Electrical Engineering Journal, Elsevier and Information Security Journal: a Global Perspective, Taylor Francis Group. He has been invited as Guest Editor of Special Issues of several publishers. He has been awarded as Top Associated Editor for 2010 and 2011, from Computers & Electrical Engineering Journal, Elsevier. He is an IEEE, Senior Member. From 2007 to 2014, he was the Council’s Chair of IEEE Greece Young Professionals. He is an Associated Member of European Network of Excellence (HiPEAC). He is a member of the IFIP Working Group 11.3 on Data and Application Security and Privacy. He is also a member of International Association for Cryptologic Research (IACR), the Technical Chamber of Greece, and the Greek Electrical Engineering Society. He has participated in the committees of up to 300 conferences organized by IEEE, ACM, IFIP, as General, Program, Publication, etc, Chair, and with other roles. He has also authored/co-authored up to 250 scientific articles, published in journals, conferences, both books, books chapters, tutorials and technical reports, in the areas of his research. He has been invited as keynote speaker to several international conferences, workshops, summer schools etc. Recently, the results of his research, have received up to 1700 citations, in the scientific and technical literature.

Preface 5
Contents 8
1 AES Datapaths on FPGAs: A State of the Art Analysis 10
1.1 Introduction 10
1.2 The AES Algorithm 11
1.2.1 SubBytes Operation 12
1.2.2 ShiftRows Operation 12
1.2.3 MixColumns Operation 13
1.2.4 Key Scheduling 13
1.3 FPGA Techniques for the AES Operations 14
1.3.1 Datapath Width 15
1.3.2 (Inv)ShiftRows Implementations: Routing, Multiplexing, and Memory Based 15
1.3.3 (Inv)SubBytes Implementations: Logic Versus Memory 17
1.3.4 Implementing the MixColumns: Logic 18
1.3.5 Implementing the InvMixColumns: Logic 20
1.3.6 Implementing the (Inv)MixColumns: Memory 21
1.3.7 Last AES Round 23
1.3.8 Types of Key Scheduling 26
1.4 FPGA Architectures for AES 27
1.4.1 Rolled Versus Unrolled Rounds 27
1.4.2 Intra Versus Inter-Pipeline 28
1.5 State of the Art Metrics 29
1.6 Conclusion 32
References 33
2 Fault Attacks, Injection Techniques and Tools for Simulation 35
2.1 Introduction 35
2.2 Fault Injection Techniques 37
2.2.1 Fault Injection Through Power Supply 38
2.2.2 Fault Injection Through Clock 38
2.2.3 Fault Injection Through Temperature 39
2.2.4 Fault Injection Through Light 39
2.2.5 Fault Injection Through Electromagnetic Fields 40
2.2.6 Fault Injection Through Focused Ion Beams 40
2.2.7 Comparison of Fault Injection Techniques 42
2.3 Fault Attacks 42
2.3.1 Algorithm Specific Attacks 42
2.3.2 Differential Fault Analysis 44
2.3.3 Tampering with the Program Flow 44
2.4 Fault Injection Simulators and Their Applicability to Fault Attacks 45
2.4.1 Weaknesses Identification with Static Analysis 46
2.4.2 High-Level Simulation with Complex Fault Models 47
2.4.3 Low-Level Virtual Machine Simulation 49
2.4.4 Transistor Level Simulation 51
2.4.5 Emulation 51
2.5 Conclusions 52
References 53
3 Recent Developments in Side-Channel Analysis on Elliptic Curve Cryptography Implementations 56
3.1 Introduction 56
3.2 Elliptic Curve Cryptography 57
3.2.1 Coordinate Systems 58
3.2.2 Forms of Elliptic Curves 58
3.3 Scalar Multiplication Algorithms 62
3.3.1 Left-to-Right Double-and-Add-Always Algorithm 63
3.3.2 Right-to-Left Double-and-Add-Always Algorithm 63
3.3.3 Montgomery Ladder 64
3.3.4 Side-Channel Atomicity 65
3.4 Side-Channel Attacks on ECC 65
3.4.1 Collision-Correlation Attacks 67
3.4.2 Horizontal Attacks and Variants 67
3.4.3 Template Attacks 69
3.4.4 Common Distinguishers 70
3.4.5 A Special Case: Online Template Attacks 72
3.5 Countermeasures 77
3.5.1 Randomization Countermeasures 78
3.5.2 OTA Countermeasures 78
References 79
4 Practical Session: Differential Power Analysis for Beginners 84
4.1 Introduction 84
4.2 Differential Power Analysis---Key Recovery 85
4.2.1 Method 86
4.2.2 Schedule of Your Work 86
4.2.3 Training Sets 86
4.2.4 Tools 87
4.3 DPA---Measurement with an Oscilloscope 93
4.3.1 Preparation of the Measurement 93
4.3.2 Compilation of Program for Measurement 97
References 98
5 Fault and Power Analysis Attack Protection Techniques for Standardized Public Key Cryptosystems 99
5.1 Introduction 99
5.2 Public Key Primitive Fault and Power Attacks and Countermeasures 101
5.2.1 Side Channel Attacks and Countermeasures 101
5.2.2 Fault Attack and Countermeasures 104
5.3 Proposed Approach 105
5.4 Security Analysis 108
5.5 Conclusion 109
References 109
6 Scan Design: Basics, Advancements, and Vulnerabilities 112
6.1 Introduction 112
6.2 DfT 113
6.2.1 Scan Design 113
6.2.2 Boundary Scan 118
6.3 Scan-Based Side-Channel Attack 119
6.3.1 Attack Principle 120
6.3.2 Advanced Encryption Standard (AES) 120
6.3.3 Traditional Scan Attack 122
6.3.4 Test-Mode-Only Scan Attack 124
6.4 Summary 130
References 130
7 Manufacturing Testing and Security Countermeasures 132
7.1 Introduction 132
7.2 Countermeasures to Scan-Based Attacks 133
7.3 Built-In Self-Test 134
7.3.1 BISTed Cryptographic Cores 135
7.3.2 Built-In Test Comparison 136
7.4 Secure Test Access Mechanism 139
7.5 Industrial Solutions 140
7.5.1 Standard DfT Weaknesses 141
7.5.2 Secure DfT and Industrial constraints 143
7.5.3 Industrial-Constraint-Aware Secure DfT 143
7.5.4 RAM/ROM Test 151
7.6 Conclusions 151
References 152
8 Malware Threats and Solutions for Trustworthy Mobile Systems Design 154
8.1 Introduction 154
8.2 Threats in Mobile Devices 155
8.3 Malware Detection Solutions 158
8.3.1 Signature-Based Detection 159
8.3.2 Static Detection 159
8.3.3 Dynamic Detection 160
8.4 Discussion 163
8.4.1 Type of Analysis 163
8.4.2 Type of Threats 163
8.4.3 Detection Techniques 167
8.4.4 Operating System 168
8.4.5 On Device Versus on Cloud Detection 169
8.4.6 Datasets 169
8.4.7 Overhead 170
8.5 Conclusions 170
References 170
9 Ring Oscillators and Hardware Trojan Detection 173
9.1 Introduction 173
9.2 Trojans and Trojan Detection Techniques 174
9.2.1 Trojan Characteristics 174
9.2.2 Trojan Taxonomies 175
9.2.3 Detection Techniques 176
9.3 Trojan Detection in True Random Number Generators 178
9.3.1 TRNG Design 178
9.3.2 Trojan Characteristics 178
9.3.3 Feasibility of a T4RNG 181
9.4 Transient-Effect Ring Oscillators for Hardware Trojan Detection 184
9.4.1 Experimental Setup 184
9.4.2 Experiments 186
9.4.3 Results and Discussion 187
9.5 Conclusions and Outlook to the Future 188
References 189
10 Notions on Silicon Physically Unclonable Functions 192
10.1 Introduction 192
10.2 A Formal Perspective on PUF 193
10.2.1 Unclonability 193
10.2.2 Uniqueness 194
10.2.3 Unpredictability 195
10.2.4 One-Way Property 195
10.2.5 Feasibility 195
10.2.6 Tamper-Evident 195
10.3 Quality Measurement on Silicon PUFs 196
10.3.1 Uniqueness 196
10.3.2 Reliability 196
10.3.3 Uniformity 197
10.3.4 Bit Aliasing 198
10.4 Categories of PUFs 198
10.4.1 Delay-Based PUF 198
10.4.2 Memory-Based PUF 204
10.5 Post-Processing Techniques 207
10.5.1 Majority Voter 207
10.5.2 Fuzzy Extractor 208
10.6 Attacks Against PUF 209
10.6.1 Model Based Attack 209
10.6.2 Side-Channel Attack 209
10.7 Conclusion 210
References 210
11 Implementation of Delay-Based PUFs on Altera FPGAs 213
11.1 Introduction 213
11.2 Altera FPGA Architecture 217
11.3 Implementing the PUF 219
11.3.1 Defining the Hardware Components 219
11.3.2 Defining the LUT Placement 223
11.3.3 Defining the LUT Routing 225
11.4 Communication Between PC and FPGA 228
11.5 Traps and Pitfalls 233
11.6 Conclusion 235
References 235
12 Implementation and Analysis of Ring Oscillator Circuits on Xilinx FPGAs 238
12.1 Introduction 238
12.2 Xilinx FPGA Fabric 240
12.3 RO Frequencies Characterization 240
12.3.1 RO Structure and Measurement Architecture 241
12.4 Result and Validation 243
12.4.1 Analysis of the Logic Surrounding the RO 243
12.4.2 Analysis of the Stages Number and Routing 246
12.4.3 Temperature Analysis 248
12.4.4 Aging Analysis 249
12.5 Conclusion 251
References 251
Index 253