Understanding Delta–Sigma Data Converters

Shanthi Pavan is a Professor of electrical engineering at the Indian Institute of Technology, India, and has been the Editor-In-Chief of the IEEE Transactions on Circuits and Systems, and a Distinguished Lecturer of the IEEE Solid State Circuits Society. He is a Fellow of the Indian National Academy of Engineering. Richard Schreier was a Division Fellow in Analog Devices Inc. and an Adjunct Professor at the University of Toronto, Canada, when he retired in 2016. From 1991-1997 he was a Professor at Oregon State University.He was named an IEEE Fellow in 2015. Gabor Temes is a Distinguished Professor Emeritus of the University of California, and Professor in the School of Electrical Engineering and Computer Science at Oregon State University, USA. He is an IEEE Life Fellow and a member of the US National Academy of Engineering.

Preface xiii 1 The Magic of Delta-Sigma Modulation 1 1.1 The Need for Oversampling Converters 1 1.2 Nyquist and Oversampling Conversion by Example 3 1.3 Higher-Order Single-Stage Noise-Shaping Modulators 11 1.4 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators 12 1.5 Mismatch Shaping in Multi-Bit Delta-Sigma Modulators 14 1.6 Continuous-Time Delta-Sigma Modulation 15 1.7 Bandpass Delta-Sigma Modulators 17 1.8 Incremental Delta-Sigma Converters 18 1.9 Delta-Sigma Digital-to-Analog Converters 18 1.10 Decimation and Interpolation 19 1.11 Specifications and Figures of Merit 19 1.12 Early History, Performance, and Architectural Trends 21 References 25 2 Sampling, Oversampling, and Noise-Shaping 27 2.1 A Review of Sampling 28 2.2 Quantization 30 2.3 Quantization Noise Reduction by Oversampling 39 2.4 Noise-Shaping 42 2.5 Nonlinear Aspects of the First-Order Delta-Sigma Modulator 52 2.6 MOD1 with DC Excitation 54 2.7 Alternative Architectures: The Error-Feedback Structure 60 2.8 The Road Ahead 60 References 61 3 Second-Order Delta-Sigma Modulation 63 3.1 Simulation of MOD2 67 3.2 Nonlinear Effects in MOD2 70 3.3 Stability of MOD2 73 3.4 Alternative Second-Order Modulator Structures 77 3.5 Generalized Second-Order Structures 80 3.6 Conclusions 82 References 82 4 High-Order Delta-Sigma Modulators 83 4.1 Signal-Dependent Stability of Delta-Sigma Modulators 85 4.2 Improving MSA in High-Order Delta-Sigma Converters 92 4.3 Systematic NTF Design 95 4.4 Noise Transfer Functions with Optimally Spread Zeros 97 4.5 Fundamental Aspects of Noise Transfer Functions 98 4.6 High-Order Single-Bit Delta-Sigma Data Converters 100 4.7 Loop Filter Topologies for Discrete-Time Delta-Sigma Converters 104 4.8 State-Space Description of Delta-Sigma Loops 114 4.9 Conclusions 115 References 115 5 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators 117 5.1 Multi-Stage Modulators 117 5.2 Cascade (MASH) Modulators 120 5.3 Noise Leakage in Cascade Modulators 123 5.4 The Sturdy-MASH Architecture 126 5.5 Noise-Coupled Architectures 128 5.6 Cross-Coupled Architectures 131 5.7 Conclusions 131 References 133 6 Mismatch-Shaping 135 6.1 The Mismatch Problem 135 6.2 Random Selection and Rotation 136 6.3 Implementation of Rotation 141 6.4 Alternative Mismatch-Shaping Topologies 145 6.5 High-Order Mismatch-Shaping 151 6.6 Generalizations 156 6.7 Transition-Error Shaping 158 6.8 Conclusions 162 References 162 7 Circuit Design for Discrete-Time Delta-Sigma ADCs 165 7.1 SCMOD2: A Second-Order Switched-Capacitor ADC 165 7.2 High-Level Design 166 7.3 Switched-Capacitor Integrator 168 7.4 Capacitor Sizing 174 7.5 Initial Verification 176 7.6 Amplifier Design 178 7.7 Intermediate Verification 186 7.8 Switch Design 191 7.9 Comparator Design 191 7.10 Clocking 195 7.11 Full-System Verification 197 7.12 High-Order Modulators 201 7.13 Multi-Bit Quantization 203 7.14 Switch Design Revisited 207 7.15 Double Sampling 209 7.16 Gain-Boosting and Gain-Squaring 211 7.17 Split-Steering and Amplifier Stacking 212 7.18 Noise in Switched-Capacitor Circuits 217 7.19 Conclusions 221 References 221 8 Continuous-Time Delta-Sigma Modulation 223 8.1 CT-MOD1 224 8.2 STF of CT-MOD1 230 8.3 Second-Order Continuous-Time Delta-Sigma Modulation 234 8.4 High-Order Continuous-Time Delta-Sigma Modulators 239 8.5 Loop-Filter Topologies 246 8.6 Continuous-Time Delta-Sigma Modulators with Complex NTF Zeros 249 8.7 Modeling of Continuous-Time Delta-Sigma Modulators for Simulation 250 8.8 Dynamic-Range Scaling 253 8.9 Design Example 255 8.10 Conclusions 258 References 258 9 Nonidealities in Continuous-Time Delta-Sigma Modulators 259 9.1 Excess Loop Delay 259 9.2 Time-Constant Variations of the Loop Filter 271 9.3 Clock Jitter in Delta-Sigma Modulators 273 9.4 Addressing Clock Jitter in Continuous-Time Delta-Sigma Modulators 285 9.5 Mitigating Clock Jitter Using FIR Feedback 287 9.6 Comparator Metastability 293 9.7 Conclusions 298 References 298 10 Circuit Design for Continuous-Time Delta-Sigma Modulators 301 10.1 Integrators 302 10.2 The Miller-Compensated OTA-RC Integrator 305 10.3 The Feedforward-Compensated OTA-RC Integrator 306 10.4 Stability of Feedforward Amplifiers 309 10.5 Device Noise in Continuous-Time Delta-Sigma Modulators 312 10.6 ADC Design 316 10.7 Feedback DAC Design 320 10.8 Systematic Design Centering 331 10.9 Loop-Filter Nonlinearities in Continuous-Time Delta-Sigma Modulators 338 10.10 Case Study of a 16-Bit Audio Continuous-Time Delta-Sigma Modulator346 10.11 Measurement Results 358 10.12 Summary 359 References 360 11 Bandpass and Quadrature Delta-Sigma Modulation 363 11.1 The Need for Bandpass Conversion 363 11.2 System Overview 366 11.3 Bandpass NTFs 367 11.4 Architectures for Bandpass Delta-Sigma Modulators 372 11.5 Bandpass Modulator Example 380 11.6 Quadrature Signals 391 11.7 Quadrature Modulation 396 11.8 Polyphase Signal Processing 402 11.9 Conclusions 404 References 405 12 Incremental Analog-to-Digital Converters 407 12.1 Motivation and Trade-Offs 407 12.2 Analysis and Design of Single-Stage IADCs 408 12.3 Digital Filter Design for Single-Stage IADCs 411 12.4 Multiple-Stage IADCs and Extended Counting ADCs 415 12.5 IADC Design Examples 416 12.6 Conclusions 422 References 423 13 Delta-Sigma DACs 425 13.1 System Architectures for Delta-Sigma DACs 425 13.2 Loop Configurations for Delta-Sigma DACs 427 13.3 Delta-Sigma DACs Using Multi-Bit Internal DACs 431 13.4 Interpolation Filtering for Delta-Sigma DACs 438 13.5 Analog Post-Filters for Delta-Sigma DACs 441 13.6 Conclusions 449 References 449 14 Interpolation and Decimation Filters 451 14.1 Interpolation Filtering 452 14.2 Example Interpolation Filter 456 14.3 Decimation Filtering 461 14.4 Example Decimation Filter 463 14.5 Halfband Filters 467 14.5.1 Saramaki Halfband Filter 469 14.6 Decimation for Bandpass Delta-Sigma ADCs 471 14.7 Fractional Rate Conversion 472 14.8 Summary 480 References 480 A Spectral Estimation 483 A.1 Windowing 484 A.2 Scaling and Noise Bandwidth 488 A.3 Averaging 491 A.4 An Example 493 A.5 Mathematical Background 495 References 498 B The Delta-Sigma Toolbox 499 C Linear Periodically Time-Varying Systems 539 C.1 Linearity and Time (In)variance 539 C.2 Linear Time-Varying Systems 541 C.3 Linear Periodically Time-Varying (LPTV) Systems 543 C.4 LPTV Systems with Sampled Outputs 547 References 559 Index 561