Toward 5G Software Defined Radio Receiver Front-Ends (eBook)

Dr. Silvian Spiridon (B.Sc.−2003, M.Sc.−2004 and Ph.D.−2011) is Principal Scientist with Broadcom Ltd. in Irvine, CA, USA. He is the project leader responsible for the design and development of wireline transceivers, high speed mixed-signal and RF circuits for cable applications. Dr. Spiridon is also a Senior Member with IEEE. His main research interest is focused on the development of a standard independent design methodology for wireless transceivers.

Foreword 10
Preface 14
Contents 16
Chapter 1: Overview of Wireless Communication in the Internet Age 19
1.1 Software Defined Radios 19
1.1.1 Digital Communications of the Internet Age 21
1.1.2 The Need for Software Defined Radios 24
1.1.3 The Software Defined Radio RF Front-End 26
1.2 Goals 27
1.3 Overview 28
References 29
Chapter 2: Defining the Optimal Architecture 31
2.1 Introduction 31
2.2 Overview of Receiver Architectures: Following the Image Rejection 32
2.2.1 Superheterodyne Receivers 32
Single Conversion 32
Dual or Double Conversion 34
2.2.2 Image Rejection Receivers 35
2.2.3 Direct Conversion Receivers 36
2.2.4 Low-IF Receivers 38
2.3 Final Decision: w/ IF vs. w/o IF (Zero-IF) 38
2.3.1 Receiver Block Schematic 40
2.4 Making Direct Conversion Receivers Ready for Monolithic Integration 41
2.4.1 Key Issues 41
2.4.2 DC Offset Compensation 42
Static Offset Removal 42
Handling Dynamic Offset 43
2.4.3 Reducing Self-Mixing 44
2.4.4 Enhanced Receiver Schematic 44
2.4.5 Architectural Evolutions: Filter-Less and Mixer-Less Front-Ends 45
2.5 Conclusions 46
References 47
Chapter 3: From High-Level Standard Requirements to Circuit-Level Electrical Specifications: A Standard-Independent Approach 48
3.1 Multi-standard Environment Impact on the SDRX Building Block Features 48
3.1.1 Multiple Frequency Bands 48
3.1.2 Variable Channel Bandwidths 48
3.1.3 Different Burst Durations 50
3.1.4 Different Modulation Schemes and Techniques 50
3.2 Introducing the Minimum SNR for Proper Signal Demodulation 50
3.3 Deriving the SDRX Noise Figure 53
3.4 Generic Blocker Diagram 53
3.5 Blocker and Interferer Impact on the SDRX Linearity 54
3.5.1 Finding the SDRX IIP2 56
3.5.2 Finding the SDRX IIP3 58
3.6 LO Phase Noise Impact on the Receiver 59
3.7 Conclusion 60
References 61
Chapter 4: Optimal Filter Partitioning 62
4.1 Defining the Channel Selection Strategy 62
4.2 Deriving the ADC Specifications 63
4.3 The Optimal Trade-Off Between LPF Order and ADC Specifications 67
4.4 Conclusion 70
References 71
Chapter 5: Smart Gain Partitioning for Noise: Linearity Trade-Off Optimization 72
5.1 Proposed Gain-Noise-Linearity Partitioning Strategy 73
5.2 Defining the SDRX Gain Settings 75
5.3 Proposed Gain Partitioning Algorithm 78
5.4 The Automated Gain Control Loop 80
5.5 Conclusion 80
Reference 81
Chapter 6: SDRX Electrical Specifications 82
6.1 Electrical Specifications 82
6.2 Noise Partitioning 82
6.3 Linearity Partitioning 85
6.4 Conclusion 87
Reference 87
Chapter 7: A System-Level Perspective of Modern Receiver Building Blocks 88
7.1 SDRX HF Part Building Blocks 88
7.1.1 The Wideband Low-Noise Amplifier 88
7.1.2 The Highly Linear Downconversion Mixer 90
7.2 SDRX LF Part Building Blocks 92
7.2.1 The LF Part Building Brick: The Fully Differential Feedback Amplifier 92
7.2.2 LF Part Modular Architecture 94
7.2.3 FDFA Power Optimization 95
7.2.4 FDFA Opamp Generic Topology 97
7.3 SDRX Bias Block 98
7.4 Baseband Noise Partitioning 100
7.4.1 Noise Excess Factor 100
7.4.2 The Trade-Off Between LF Part Power Consumption and Area 102
7.4.3 Noise Partitioning 103
7.5 Conclusion 104
References 105
Chapter 8: Conclusions and Future Developments 107
8.1 Conclusions 107
8.2 Future Developments 110
References 111